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Conception de transistors MOS haute tension en technologie CMOS 0,18 um sur substrat "silicium sur isolant" (SOI pour les nouvelles gégérations de circuits intégrés de puissance

Gaëtan Toulon 1
1 LAAS-ISGE - Équipe Intégration de Systèmes de Gestion de l'Énergie
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : Power integrated circuits combine on a same ship digital logic functions from CMOS circuits associated with power switches such as DMOS transistors. The demand for more and more complex applications requires finer lithography in order to increase the CMOS components density. The evolution of CMOS technology requires developing new DMOS components compatible with the power integrated circuits. This thesis focuses on the conception of high voltage LDMOS transistors (120V) compatible with a 0.18 µm CMOS process based on a "silicon on insulator" substrate. Several N and P channel LDMOS transistor designs were studied and optimised in terms of "breakdown voltage / specific on-state resistance" trade-off from finite element TCAD simulations. The performances of the structures were compared in terms of figure of merit Ron×Qg, which is the product between the on-state resistance and the gate charge, and in terms of safe operating area. The best STI-DLMOS and SJ-LDMOS (N-type) and R-PLDMOS (P-type) transistors exhibit static and dynamic performances comparable and sometime superior to those of the state-of-the-art power transistors. Different experimental measurements carried out on LDMOSFETs manufactured by ATMEL and compared with simulations, allowed to validate the simulation results performed in this thesis.
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  • HAL Id : tel-00566469, version 1

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Gaëtan Toulon. Conception de transistors MOS haute tension en technologie CMOS 0,18 um sur substrat "silicium sur isolant" (SOI pour les nouvelles gégérations de circuits intégrés de puissance. Micro et nanotechnologies/Microélectronique. Université Paul Sabatier - Toulouse III, 2010. Français. ⟨tel-00566469⟩

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