Skip to Main content Skip to Navigation

Intégration monolithique de matériaux III-V et de Ge sur Si en utilisant des buffers oxydes cristallins

Jun Cheng 1
1 INL - H&N - INL - Hétéroepitaxie et Nanostructures
INL - Institut des Nanotechnologies de Lyon
Abstract : The monolithic integration of III-V semiconductors and Ge on Si is a major issue of heteroepitaxy that gave rise to extensive researches for over twenty years. Firstly because it allows combining the optoelectronic functionalities with industry standard CMOS, which can replace the metal interconnects by optical interconnects in integrated circuits. Moreover, the integration of III-V semiconductors or Ge on Si would significantly reduce the manufacturing cost of solar cells for the niche space market.The direct heteroepitaxy of III-V semiconductor on Si is difficult because of the great lattice mismatch and different thermal expansion coefficient between these materials. Various methods have been proposed in the last twenty years, especially, the solutions based on sticking technologies such as‘Smart Cut TM’ offer excellent results, but is limited by its less flexibility and higher cost.The objective of this thesis is to propose a solution that consists in integrating monolithicallyIII-V semiconductors on Si by using the buffer layers of oxides. We have firstly demonstrated theoretically and experimentally that for the systems semiconductor/oxide, the semiconductor grows with his lattice parameter from the beginning of the growth and doesn’t contain any defaults associated with the plastic relaxation, the difference of the lattice parameter is fully accommodated bythe interfacial dislocations, thus, it’s a priori possible to obtain a flat 2D layer of semiconductor/oxideby the coalescence of the islands without extended defects, presenting the lattice parameter of the semiconductor from the beginning of the growth, providing that no defect is formed during the coalescence of islands.The second part is dedicated to the coalescence of islands for the system InP/SrTiO3/Si, a 3-step strategy was used to favor the coalescence of islands InP on SrTiO3/Si, the coalesced InP layershows good crystalline quality and excellent surface quality. However, we observed the presence of defects, including anti-phase boundaries and microtwins. Despite these defects in the layer, we have realized a quantum well InP/InAsP grown on SrTiO3/Si, it presents a better quality crystal and optical compared with a reference quantum well InP/InAsP that grows directly on Si.
Keywords : GaAs Semiconductors InP
Document type :
Complete list of metadatas
Contributor : Abes Star :  Contact
Submitted on : Friday, February 11, 2011 - 5:19:10 PM
Last modification on : Wednesday, July 8, 2020 - 12:43:56 PM
Long-term archiving on: : Thursday, May 12, 2011 - 2:57:41 AM


Version validated by the jury (STAR)


  • HAL Id : tel-00565337, version 1


Jun Cheng. Intégration monolithique de matériaux III-V et de Ge sur Si en utilisant des buffers oxydes cristallins. Autre. Ecole Centrale de Lyon, 2010. Français. ⟨NNT : 2010ECDL0024⟩. ⟨tel-00565337⟩



Record views


Files downloads