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Regulation of power amplifiers under VSWR conditions in CMOS 65nm for 60GHz applications

Abstract : With the emergence of mass-market applications, such as Wireless-HD, low-cost CMOS technologies are requested to democratize the use of mmW frequencies. However, before being commercialized, mmW transmitters have to ensure sufficient reliability. One major reliability issue lies in the impedance mismatch between the power amplifier (PA) and the antenna, which can result from wave propagation obstacles in the close vicinity of the antenna. Such impedance mismatch generates standing waves, which can cause irreversible damage on the power amplifier. This thesis aims to propose an innovating regulation architecture that could protect the power amplifier from such deterioration and optimize its performance. By integrating several power detectors between the PA and the antenna, the impedance mismatch can be evaluated. Using this information, a digital regulation loop could then elaborate a complete strategy in order to optimize the PA performance. This thesis notably investigates the power detection circuits, which should sense the antenna impedance mismatch. A circuit realization in 65nm CMOS process from STMicroelectronics shows that the power detector provides 25dB dynamic range at 60GHz and is able to detect up to 3:1 VSWR. A second circuit realization integrates a power amplifier, the power detection circuits and data converters (ADC & DAC). The regulation loop acts on the power amplifier gain to keep a constant PA output power whatever the antenna impedance is. A second loop is also integrated, which protects the PA from destruction. This thesis also covers two alternative projects developed simultaneously to the VSWR-regulated PA architecture. First, a novel architecture of Logarithmic-Analog-to-Digital-Converter is proposed, which is based on the progressive compression architecture of logarithmic amplifier. Then the simulation aspect of the VSWR-regulated PA is investigated through an ADS co-simulation of an RF/mmW PA with its mixed-signal regulation loop.
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Contributor : Jean Gorisse Connect in order to contact the contributor
Submitted on : Friday, February 4, 2011 - 1:56:30 PM
Last modification on : Tuesday, November 23, 2021 - 9:45:00 AM
Long-term archiving on: : Thursday, May 5, 2011 - 2:31:18 AM


  • HAL Id : tel-00563235, version 1


Jean Gorisse. Regulation of power amplifiers under VSWR conditions in CMOS 65nm for 60GHz applications. Micro and nanotechnologies/Microelectronics. Université des Sciences et Technologie de Lille - Lille I, 2010. English. ⟨tel-00563235⟩



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