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Etude de la conduction électrique dans les diélectriques à forte permittivité utilisés en microélectronique

Abstract : Since 45nm node, the replacement of conventional SiO2 oxide by a high-permittivity dielectric has become mandatory to continue Moore's law : such material enables to keep high gate capacitance values while reducing gate leakage current. However, a complete understanding of gate leakage mechanisms through high-κ-based gate stacks has not been reached yet. This thesis analyses electrical conduction in interfacial layer - high-κ dielectric - metal gate stacks. Quantum confinement modeling is first presented, by means of self-consistent Poisson-Schrödinger resolution accounting for both wavefunction penetration into the gate stack as well as valence band anisotropy. Then, a complete experimental study highlights the physical mechanisms responsible for gate leakage current, relying on the Ig(Vg) and C(Vg) electrical characteristics of various nMOS gate stacks with different dielectric thicknesses, measured at low and high temperature. Original models for gate current computation are also proposed, in order to establish both HfO2 tunneling parameters and band structure within an experimental approach. Finally, the influence of La- and Mg- capping layers on gate leakage is studied, and the presence of a dipole responsible for threshold voltage shift is experimentaly confirmed.
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Contributor : Jean Coignus <>
Submitted on : Wednesday, January 26, 2011 - 4:34:34 PM
Last modification on : Thursday, November 19, 2020 - 1:00:36 PM
Long-term archiving on: : Wednesday, April 27, 2011 - 3:16:53 AM


  • HAL Id : tel-00557752, version 2



Jean Coignus. Etude de la conduction électrique dans les diélectriques à forte permittivité utilisés en microélectronique. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨tel-00557752v2⟩



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