D. Hardy and I. Puaut, WCET analysis of instruction cache hierarchies, Journal of Systems Architecture, vol.57, issue.7, 2010.
DOI : 10.1016/j.sysarc.2010.08.007

URL : https://hal.archives-ouvertes.fr/hal-00639454

B. Lesage, D. Hardy, and I. Puaut, Shared data cache conflicts reduction for WCET computations in multi-core architectures, Proceedings of the 18th Real-Time and Network Systems, 2010.

D. Hardy, T. Piquet, and I. Puaut, Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches, Proceedings of the 30th Real-Time Systems Symposium, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00380298

D. Hardy and I. Puaut, Estimation of cache related migration delays for multi-core processors with shared instruction caches, Proceedings of the 17th Real-Time and Network Systems, pp.45-54, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00441959

B. Lesage, D. Hardy, and I. Puaut, WCET analysis of multi-level setassociative data caches, 9th Intl. Workshop on Worst- Case Execution Time (WCET) Analysis Schloss Dagstuhl -Leibniz-Zentrum fuer Informatik, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00531218

D. Hardy and I. Puaut, WCET analysis of multi-level non-inclusive setassociative instruction caches, Proceedings of the 29th Real-Time Systems Symposium, pp.456-466, 2008.

D. Hardy and I. Puaut, Predictable Code and Data Paging for Real Time Systems, 2008 Euromicro Conference on Real-Time Systems, pp.266-275, 2008.
DOI : 10.1109/ECRTS.2008.16

I. Puaut and D. Hardy, Predictable Paging in Real-Time Systems: A Compiler Approach, 19th Euromicro Conference on Real-Time Systems (ECRTS'07), pp.169-178, 2007.
DOI : 10.1109/ECRTS.2007.25

N. B. Aissa, G. Grimaud, and D. Simplot-ryl, A distributed and verifiable loop bounding algorithm for wcet computation on constrained embedded systems, Proceedings of the 14th International Conference on Real-Time and Network Systems, 2006.

N. B. Aissa, C. Rippert, D. Deville, and G. Grimaud, A distributed WCET computation scheme for smart card operating systems, 4th international workshop on Worst Case Execution Time Analysis, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00309686

H. Al-zoubi, A. Milenkovic, and M. Milenkovic, Performance evaluation of cache replacement policies for the SPEC CPU2000 benchmark suite, Proceedings of the 42nd annual Southeast regional conference on , ACM-SE 42, pp.267-272, 2004.
DOI : 10.1145/986537.986601

R. Arnold, F. Mueller, D. Whalley, and M. Harmon, Bounding worst-case instruction cache performance, Proceedings Real-Time Systems Symposium REAL-94, pp.172-181, 1994.
DOI : 10.1109/REAL.1994.342718

N. Audsley, A. Burns, M. Richardson, K. Tindell, and A. J. Wellings, Applying new scheduling theory to static priority pre-emptive scheduling, Software Engineering Journal, vol.8, issue.5, pp.284-292, 1993.
DOI : 10.1049/sej.1993.0034

J. Baer and W. Wang, On the inclusion properties for multi-level cache hierarchies, ISCA'88 : Proceedings of the 15th Annual International Symposium on Computer architecture, pp.73-80, 1988.

C. Ballabriga, Vérification de contraintes temporelles strictes sur des programmes par composition d'analyses partielles, 2010.

C. Ballabriga and H. Cassé, Improving the first-miss computation in setassociative instruction caches, Euromicro Conference on Real-Time Systems (ECRTS), 2008.

C. Ballabriga, H. Casse, and P. Sainrat, An improved approach for setassociative instruction cache partial analysis, SAC '08 : Proceedings of Bibliographie the 2008 ACM symposium on Applied computing, pp.360-367, 2008.

I. Bate and R. Reutemann, Worst-case execution time analysis for dynamic branch predictors, Proceedings. 16th Euromicro Conference on Real-Time Systems, 2004. ECRTS 2004., pp.215-222, 2004.
DOI : 10.1109/EMRTS.2004.1311023

L. A. Belady, A study of replacement algorithms for a virtual-storage computer, IBM Systems Journal, vol.5, issue.2, pp.78-101, 1966.
DOI : 10.1147/sj.52.0078

C. Berg, PLRU cache domino effects, 6th IntlCase Execution Time (WCET) Analysis, Dresden, number 06902 in Dagstuhl Seminar Proceedings. Internationales Begegnungs-und Forschungszentrum fuer Informatik (IBFI), 2006.

E. Bini, G. C. Buttazzo, and G. M. Buttazzo, Rate monotonic analysis: the hyperbolic bound, IEEE Transactions on Computers, vol.52, issue.7, pp.933-942, 2003.
DOI : 10.1109/TC.2003.1214341

J. Blieberger, T. Fahringer, and B. Scholz, Symbolic cache analysis for real-time systems, Real-Time Systems, vol.18, issue.2/3, pp.181-215, 2000.
DOI : 10.1023/A:1008193114940

C. Burguière, J. Reineke, and S. Altmeyer, Cache-related preemption delay computation for set-associative caches?pitfalls and solutions, Proceedings of 9th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2009.

C. Burguière, Modéliser la prédiction de branchement pour le calcul de temps d'exécution pire-cas, 2008.

L. Burkholder, The halting problem, ACM SIGACT News, vol.18, issue.3, pp.48-60, 1987.
DOI : 10.1145/24658.24665

M. Campoy, A. P. Ivars, and J. V. Mataix, Static use of locking caches in multitask preemptive real-time systems, Proceedings of IEEE/IEE Real-Time Embedded Systems Workshop (Satellite of the IEEE Real-Time Systems Symposium), 2001.

J. Carpenter, S. Funk, P. Holman, A. Srinivasan, J. Anderson et al., A categorization of real-time multiprocessor scheduling problems and algorithms, Handbook on Scheduling Algorithms, Methods, and Models, 2004.

S. Chattopadhyay and A. Roychoudhury, Unified Cache Modeling for WCET Analysis and Layout Optimizations, 2009 30th IEEE Real-Time Systems Symposium, pp.47-56, 2009.
DOI : 10.1109/RTSS.2009.20

A. Colin and I. Puaut, Worst case execution time analysis for a processor withbranch prediction. Real-Time Syst, pp.249-274, 2000.

A. Colin and I. Puaut, A modular and retargetable framework for treebased WCET analysis, Euromicro Conference on Real-Time Systems (ECRTS), pp.37-44, 2001.

P. Cousot and R. Cousot, Abstract interpretation, Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages , POPL '77, pp.238-252, 1977.
DOI : 10.1145/512950.512973

URL : https://hal.archives-ouvertes.fr/inria-00528590

P. Cousot and R. Cousot, Basic Concepts of Abstract Interpretation, pp.359-366, 2004.
DOI : 10.1007/978-1-4020-8157-6_27

C. Cullmann, C. Ferdinand, G. Gebhard, D. Grund, C. Maiza et al., Predictability considerations in the design of multi-core embedded systems, Proceedings of Embedded Real Time Software and Systems, 2010.

J. Deverge and I. Puaut, WCET-Directed Dynamic Scratchpad Memory Allocation of Data, 19th Euromicro Conference on Real-Time Systems (ECRTS'07), pp.179-190, 2007.
DOI : 10.1109/ECRTS.2007.37

J. Deverge, Contributions à l'analyse du comportement temporel de la hiérarchie mémoire pour l'estimation du pire temps d'exécution, 2008.

H. Dybdahl and P. Stenström, Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination, Asia-Pacific Computer Systems Architecture Conference, pp.52-66, 2006.
DOI : 10.1007/11859802_6

J. Engblom, Processor pipelines and static worst-case execution time analysis

M. Farrens, G. Tyson, J. Matthews, and A. R. Pleszkun, A modified approach to data cache management, Proceedings of the 28th Annual International Symposium on Microarchitecture, pp.93-103, 1995.

C. Ferdinand, Cache behavior prediction for real-time systems, 1997.

C. Ferdinand and R. Wilhelm, On predicting data cache behavior for realtime systems, LCTES '98 : Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems, pp.16-30, 1998.

S. Ghosh, M. Martonosi, and S. Malik, Cache miss equations: a compiler framework for analyzing and tuning memory behavior, ACM Transactions on Programming Languages and Systems, vol.21, issue.4, pp.703-746, 1999.
DOI : 10.1145/325478.325479

J. Goossens, S. Baruah, and S. Funk, Real-time scheduling on uniform multiprocessors, Proceedings of the 10th International Conference on Real-Time Systems, pp.189-204, 2002.

D. Hardy, T. Piquet, and I. Puaut, Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches, Proceedings of the 30th Real-Time Systems Symposium, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00380298

D. Hardy and I. Puaut, Predictable Code and Data Paging for Real Time Systems, 2008 Euromicro Conference on Real-Time Systems, pp.266-275, 2008.
DOI : 10.1109/ECRTS.2008.16

D. Hardy and I. Puaut, WCET analysis of multi-level non-inclusive setassociative instruction caches, Proceedings of the 29th Real-Time Systems Symposium, pp.456-466, 2008.

D. Hardy and I. Puaut, Estimation of cache related migration delays for multi-core processors with shared instruction caches, Proceedings of the 17th Real-Time and Network Systems, pp.45-54, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00441959

D. Hardy and I. Puaut, WCET analysis of instruction cache hierarchies, Journal of Systems Architecture, vol.57, issue.7, 2010.
DOI : 10.1016/j.sysarc.2010.08.007

URL : https://hal.archives-ouvertes.fr/hal-00639454

R. Heckmann, M. Langenbach, S. Thesing, and R. Wilhelm, The influence of processor architecture on the design and the results of WCET tools, Proceedings of the IEEE, p.7, 2003.
DOI : 10.1109/JPROC.2003.814618

M. D. Hill and A. J. Smith, Evaluating associativity in CPU caches, IEEE Transactions on Computers, vol.38, issue.12, pp.1612-1630, 1989.
DOI : 10.1109/12.40842

M. J. Irwin, Shared caches in multicores : The good, the bad, and the ugly, ISCA'10 : Proceedings of the 37th annual International Symposium on Computer and Architecture, p.234, 2010.

N. P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, SIGARCH Comput. Archit. News, issue.3a, pp.18364-373, 1990.

J. L. Ford and D. R. Fulkerson, Maximal flow through a network, can. j. math, pp.399-404, 1956.

M. Lee, S. L. Min, H. Shin, C. S. Kim, and C. Y. Park, Threaded prefetching : A new instruction memory hierarchy for real-timesystems. Real- Time Syst, and I. Puaut. WCET analysis of multi-level setassociative data caches, 9th Intl. Workshop on Worst- Case Execution Time (WCET) Analysis Schloss Dagstuhl -Leibniz-Zentrum fuer Informatik, pp.47-65, 1997.

B. Lesage, D. Hardy, and I. Puaut, Shared data cache conflicts reduction for WCET computations in multi-core architectures, Proceedings of the 18th Real-Time and Network Systems, 2010.

X. Li, A. Roychoudhury, and T. Mitra, Modeling out-of-order processors for WCET estimation. Real-Time Systems Journal, 2006.

Y. Li, V. Suhendra, Y. Liang, T. Mitra, and A. Roychoudhury, Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores, 2009 30th IEEE Real-Time Systems Symposium, pp.57-67, 2009.
DOI : 10.1109/RTSS.2009.32

Y. S. Li and S. Malik, Performance analysis of embedded software using implicit path enumeration, LCTES '95 : Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers , & tools for real-time systems, pp.88-98, 1995.

Y. S. Li, S. Malik, and A. Wolfe, Cache modeling for real-time software: beyond direct mapped instruction caches, 17th IEEE Real-Time Systems Symposium, p.254, 1996.
DOI : 10.1109/REAL.1996.563722

C. L. Liu and J. W. Layland, Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, Journal of the ACM, vol.20, issue.1, pp.46-61, 1973.
DOI : 10.1145/321738.321743

P. Lokuciejewski, H. Falk, and P. Marwedel, WCET-driven Cache-based Procedure Positioning Optimizations, 2008 Euromicro Conference on Real-Time Systems, 2008.
DOI : 10.1109/ECRTS.2008.20

P. Lokuciejewski, H. Falk, P. Marwedel, and H. Theiling, WCET-driven, code-size critical procedure cloning, Proceedings of the 11th international workshop on Software & compilers for embedded systems, SCOPES '08, pp.21-30, 2008.
DOI : 10.1145/1361096.1361100

P. Lokuciejewski and P. Marwedel, Combining Worst-Case Timing Models, Loop Unrolling, and Static Loop Analysis for WCET Minimization, 2009 21st Euromicro Conference on Real-Time Systems, pp.35-44, 2009.
DOI : 10.1109/ECRTS.2009.9

T. Lundqvist and P. Stenström, An integrated path and timing analysis method based on cycle-level symbolic execution. Real-Time Syst, pp.183-207, 1999.

T. Lundqvist and P. Stenström, A method to improve the estimated worstcase performance of data caching, Proceedings of the 6th International Conference on Real-Time Computing Systems and Applications, pp.255-262, 1999.

T. Lundqvist and P. Stenström, Timing anomalies in dynamically scheduled microprocessors, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054), pp.12-21, 1999.
DOI : 10.1109/REAL.1999.818824

A. Marref and G. Bernat, Towards predicated WCET analysis Workshop on Worst-Case Execution Time (WCET) Analysis Schloss Dagstuhl -Leibniz-Zentrum fuer Informatik, Germany. also published in print by Austrian Computer Society (OCG) under, 8th Intl, 2008.

S. Mcfarling, Program optimization for instruction caches, ACM SIGARCH Computer Architecture News, vol.17, issue.2, pp.183-191, 1989.
DOI : 10.1145/68182.68200

P. Michaud, Replacement policies for shared caches on symmetric multicores, Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers, HiPEAC '11, 2008.
DOI : 10.1145/1944862.1944890

URL : https://hal.archives-ouvertes.fr/inria-00531188

F. Mueller, Static cache simulation and its applications, 1994.

F. Mueller, Timing predictions for multi-level caches, ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, pp.29-36, 1997.

F. Mueller, Timing analysis for instruction caches, Real-Time Systems, vol.18, issue.2/3, pp.217-247, 2000.
DOI : 10.1023/A:1008145215849

H. S. Negi, T. Mitra, and A. Roychoudhury, Accurate estimation of cacherelated preemption delay, CODES+ISSS '03 : Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp.201-206, 2003.

H. Ozaktas, K. Heydemann, C. Rochange, and H. Cassé, Impact of Code Compression on Estimated Worst-Case Execution Times, International Conference on Real-Time and Network Systems (RTNS), pp.55-64, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00441964

M. Paolieri, E. Qui-nones, F. J. Cazorla, G. Bernat, and M. Valero, Hardware support for WCET analysis of hard real-time multicore systems, ISCA '09 : Proceedings of the 36th annual international symposium on Computer architecture, pp.57-68, 2009.

T. Piquet, Gestion consciente du contenu de la hiérarchie mémoire, 2008.

T. Piquet, O. Rochecouste, and A. Seznec, Exploiting Single-Usage for Effective Memory Management, ACSAC '07 : Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture, pp.90-101, 2007.
DOI : 10.1007/978-3-540-74309-5_11

G. N. Prasanna, Cache structure and method for improving worst case execution time. Patent Pending, pp.599-600, 2001.

I. Puaut, WCET-Centric Software-controlled Instruction Caches for Hard Real-Time Systems, 18th Euromicro Conference on Real-Time Systems (ECRTS'06), 2006.
DOI : 10.1109/ECRTS.2006.32

I. Puaut and D. Decotigny, Low-complexity algorithms for static cache locking in multitasking hard real-time systems, 23rd IEEE Real-Time Systems Symposium, 2002. RTSS 2002., p.114, 2002.
DOI : 10.1109/REAL.2002.1181567

P. Puschner and A. Burns, A review of worst-case execution-time analysis, Real-Time Systems, vol.18, issue.2/3, pp.115-128, 2000.
DOI : 10.1023/A:1008119029962

P. Puschner and C. Koza, Calculating the maximum execution time of real-time programs, Real-Time Systems, vol.20, issue.1, pp.159-176, 1989.
DOI : 10.1007/BF00571421

P. Puschner and A. V. Schedl, Computing maximum task execution times ? a graph based approach, Proceedings of IEEE Real-Time Systems Symposium, pp.67-91, 1997.

M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely, and J. Emer, Adaptive insertion policies for high performance caching, ISCA '07 : Proceedings of the 34th annual international symposium on Computer architecture, pp.381-391, 2007.

H. Ramaprasad and F. Mueller, Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns, 11th IEEE Real Time and Embedded Technology and Applications Symposium, pp.148-157, 2005.
DOI : 10.1109/RTAS.2005.12

H. Ramaprasad and F. Mueller, Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), pp.71-80, 2006.
DOI : 10.1109/RTAS.2006.14

J. Reineke and D. Grund, Relative competitive analysis of cache replacement policies, LCTES '08 : Proceedings of the 2008 ACM SIGPLAN- SIGBED conference on Languages, compilers, and tools for embedded systems, pp.51-60, 2008.

J. Reineke, D. Grund, C. Berg, and R. Wilhelm, Timing predictability of cache replacement policies. Real-Time Syst, pp.99-122, 2007.

J. Reineke, B. Wachter, S. Thesing, R. Wilhelm, I. Polian et al., A definition and classification of timing anomalies, Proceedings of 6th International Workshop on Worst-Case Execution Time (WCET) Analysis, 2006.

H. G. Rice, Classes of recursively enumerable sets and their decision problems . Transactions of the, pp.358-366, 1953.

C. Rochange and P. Sainrat, Code padding to improve the WCET calculability, International Conference on Real-Time and Network Systems (RTNS), pp.159-168, 2006.

J. Rosen, A. Andrei, P. Eles, and Z. Peng, Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip, 28th IEEE International Real-Time Systems Symposium (RTSS 2007), pp.49-60, 2007.
DOI : 10.1109/RTSS.2007.24

A. Sarkar, F. Mueller, H. Ramaprasad, and S. Mohan, Push-assisted migration of real-time tasks in multi-core processors, LCTES '09 : Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, pp.80-89, 2009.

J. E. Sasinowski and J. K. Strosnider, A dynamic programming algorithm for cache memory partitioning for real-time systems, IEEE Transactions on Computers, vol.42, issue.8, pp.997-1001, 1993.
DOI : 10.1109/12.238493

A. Schr?ver, Theory of linear and integer programming, 1986.

R. Sen and Y. N. Srikant, WCET estimation for executables in the presence of data caches, Proceedings of the 7th ACM & IEEE international conference on Embedded software , EMSOFT '07, pp.203-212, 2007.
DOI : 10.1145/1289927.1289960

A. Seznec, A case for two-way skewed-associative caches, ISCA '93 : Proceedings of the 20th annual international symposium on Computer architecture, pp.169-178, 1993.

A. J. Smith, Cache Memories, ACM Computing Surveys, vol.14, issue.3, pp.473-530, 1982.
DOI : 10.1145/356887.356892

J. Staschulat, S. Schliecker, and R. Ernst, Scheduling Analysis of Real-Time Systems with Precise Modeling of Cache Related Preemption Delay, 17th Euromicro Conference on Real-Time Systems (ECRTS'05), pp.41-48, 2005.
DOI : 10.1109/ECRTS.2005.26

V. Suhendra and T. Mitra, Exploring locking & partitioning for predictable shared caches on multi-cores, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.300-303, 2008.
DOI : 10.1145/1391469.1391545

C. P. Thacker, Improving the future by examining the past, ISCA'10 : Proceedings of the 37th annual International Symposium on Computer and Architecture, p.348, 2010.

H. Theiling, C. Ferdinand, and R. Wilhelm, Fast and precise WCET prediction by separated cache and path analyses. Real-Time Systems Journal, pp.157-179, 2000.

X. Vera, B. Lisper, and J. Xue, Data cache locking for higher program predictability, SIGMETRICS '03 : Proceedings of the 2003 ACM SIGME- TRICS international conference on Measurement and modeling of computer systems, pp.272-282, 2003.

J. Wegener and F. Mueller, A comparison of static analysis and evolutionary testing for the verification of timing constraints. Real-Time Syst, pp.241-268, 2001.

I. Wenzel, R. Kirner, P. Puschner, and B. Rieder, Principles of Timing Anomalies in Superscalar Processors, Fifth International Conference on Quality Software (QSIC'05), pp.295-306, 2005.
DOI : 10.1109/QSIC.2005.49

R. T. White, F. Mueller, C. Healy, D. Whalley, and M. Harmon, Timing analysis for data and wrap-around fill caches. Real-Time Syst, pp.209-233, 1999.

R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing et al., The Determination of Worst-Case Execution Times?Overview of the Methods and Survey of Tools, TECS), 2008.

R. Wilhelm, D. Grund, J. Reineke, M. Schlickling, M. Pister et al., Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, issue.7, pp.966-978, 2009.
DOI : 10.1109/TCAD.2009.2013287

N. Williams, B. Marre, P. Mouy, and M. Roger, PathCrawler: Automatic Generation of Path Tests by Combining Static and Dynamic Analysis, EDCC, pp.281-292, 2005.
DOI : 10.1007/11408901_21

J. Yan and W. Zhang, WCET analysis of instruction caches with prefetching, ACM SIGPLAN Notices, vol.42, issue.7, pp.175-184, 2007.
DOI : 10.1145/1273444.1254801

J. Yan and W. Zhang, WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium, pp.80-89, 2008.
DOI : 10.1109/RTAS.2008.6

W. Zhao, W. Kreahling, D. Whalley, C. Healy, and F. Mueller, Improving WCET by applying worst-case path optimizations. Real-Time Syst, pp.129-152, 2006.
DOI : 10.1007/s11241-006-8643-4

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.72.3579

Y. Zheng, B. T. Davis, and M. Jordan, Performance evaluation of exclusive cache hierarchies, IEEE International Symposium on, ISPASS Performance Analysis of Systems and Software, 2004, pp.89-96, 2004.
DOI : 10.1109/ISPASS.2004.1291359