Development of high performance hardware architectures for multimedia applications

Shafqat Khan 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
Inria Rennes – Bretagne Atlantique , IRISA-D3 - ARCHITECTURE
Abstract : The computational requirements of the processors are increasing tremendously with the increase in the complexity of applications. Among these applications, multimedia represents the class of applications which requires lot of computations on low precision pixels. These applications include motion estimation, discrete cosine transform, image filtering etc. The processing requirements of multimedia applications can be fulfilled by performing parallel computations on input pixel data. Subword parallelism (SWP) is one of the best options to exploit data level parallelism that exist in the applications. In SWP, rather than wasting the word oriented data path, parallel operations are executed on packed subwords. SWP increases the performance of the processor especially for multimedia applications with low precision pixel data. Coordination between pixel sizes in multimedia applications and subword sizes in SWP operators further increases the performance through a better resource utilization. In this thesis, reconfigurable SWP arithmetic operators are proposed for multimedia applications. In the proposed basic SWP operators, parallelism is obtained by using multimedia oriented subword sizes (8, 10, 12 or 16-bit) rather than classical subword sizes (8, 16 or 32-bit etc.). Compared to classical SWP operators, the multimedia SWP operator utilizes the available resources more efficiently when working on different video applications. SWP arithmetic operators are then used to design reconfigurable operators for multimedia applications. In the proposed reconfigurable operators, reconfiguration is provided at both the data size level and the operation level without any reconfiguration time overheads. These operators can perform a variety of basis as well as multimedia operations on different size pixel data. These operators can be used as co-processors to enhance the performance for multimedia applications. Along with parallelism, the internal computational speed of the different arithmetic units is improved by introducing the redundant number system in the SWP architectures. Redundant number system provides a carry propagation free addition which ultimately increases the speed of different arithmetic operations. The performance of SWP operators are verified on different multimedia kernels.
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Shafqat Khan. Development of high performance hardware architectures for multimedia applications. Micro and nanotechnologies/Microelectronics. Université Rennes 1, 2010. English. ⟨tel-00554668⟩

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