Fast Simulation Strategies and Adaptive DVFS Algorithm for Low Power MPSoCs

Abstract : SoC (System on Chip) devices have seen their capabilities increasing continuously allowing these devices and the applications running on them to become more and more complex thanks to the integration technology. Many of these devices operate unplugged, but as the battery technology does not scale with integration, both the software and the hardware of these devices must be energy efficient. We propose in this thesis a software algorithm that tries to save energy by modifying the processors frequencies and voltage when the system utilization permits. This algorithm does not need any input from applications. In order to test and determine the effectiveness of the proposed energy saving algorithm we need fast and accurate simulation platforms that support individual frequency change for each processor or subsystem. The right level of abstraction for estimating power consumption by simulation is not obvious. We firstly defined a high level simulation strategy that combines the accuracy of the hardware focused simulators with the speed of the behavior focused simulators. When more accurate estimations are required, a cycle accurate/bit accurate simulation must be used. However, to accelerate simulation, static scheduling strategies not compatible with DVFS are used. We defined two new approaches for supporting DVFS in this context.
Complete list of metadatas
Contributor : Lucie Torella <>
Submitted on : Tuesday, November 30, 2010 - 1:40:00 PM
Last modification on : Wednesday, May 16, 2018 - 6:30:04 PM
Long-term archiving on : Friday, October 26, 2012 - 5:05:38 PM


  • HAL Id : tel-00541337, version 1




M. Gligor. Fast Simulation Strategies and Adaptive DVFS Algorithm for Low Power MPSoCs. Micro and nanotechnologies/Microelectronics. Institut National Polytechnique de Grenoble - INPG, 2010. English. ⟨tel-00541337⟩



Record views


Files downloads