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Multi-Level Fault-Tolerance in Networks-on-Chip

Abstract : With the continuous shrinking of technology features and the growing complexity of systems-on-chip, networks-on-chip have emerged as the most promising solution for the on-chip communication system. However, current systems-on-chip are subject to different factors (process variation, electromigration, crosstalk, environmental constraints and permanent defects in the case of 3D integration) that can perturb their logical and temporal operation and eventually lead to failures of the communication system or of different components of heterogeneous systems comprised of microprocessors, ASICs, memories etc. In this thesis different complementary approaches to deal with these problems are addressed, including techniques at data link level such as error detection combined with correction or data retransmission, fault tolerant routing algorithms for 3D topologies, and rollback recovery of the application after possible failures, by the use of checkpoints.
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https://tel.archives-ouvertes.fr/tel-00541260
Contributor : Lucie Torella <>
Submitted on : Tuesday, November 30, 2010 - 11:30:02 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Tuesday, March 1, 2011 - 2:47:36 AM

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  • HAL Id : tel-00541260, version 1

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C. Rusu. Multi-Level Fault-Tolerance in Networks-on-Chip. Micro and nanotechnologies/Microelectronics. Institut National Polytechnique de Grenoble - INPG, 2010. English. ⟨tel-00541260⟩

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