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Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles

Abstract : The arrival of multiprocessor chips rises again some questions about the way of writing programs, which must then include a high degree of parallelism. We tackle this problem via two orthogonal approaches. First, via the work-stealing paradigm, for which we perform a study targeting on the first hand to seek for simple architectural characteristics giving the best performances for an implementation of this paradigm; and on the second hand to show that the overhead compared to a static parallelization is low, while allowing performances improvement thanks to dynamic load balancing. This question is nevertheless especially tackled via the transaction based programming paradigm -- sequence of instructions executing atomically from the other cores' point of view. Supporting this abstraction requires the implementation of a system called TM, often complex, either software or hardware. The study focuses first on the comparison between two hardware TM systems based on different architecture choices (cache coherence protocol), and then on the impact on performances of several conflict resolution policies, in other words the actions to be taken when two or more transactions try to access the same pieces of data.
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https://tel.archives-ouvertes.fr/tel-00532794
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Submitted on : Thursday, November 4, 2010 - 2:09:08 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Friday, October 26, 2012 - 2:55:34 PM

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  • HAL Id : tel-00532794, version 1

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Quentin L. Meunier. Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles. Autre [cs.OH]. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨tel-00532794⟩

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