K. Martin, C. Wolinski, K. Kuchcinski, F. Charot, and A. , Floc'h : Constraint- Driven Identification of Application Specific Instructions in the DURASE system, SAMOS '09: Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.194-203, 2009.

K. Martin, C. Wolinski, K. Kuchcinski, F. Charot, and A. , Floc'h : Constraint- Driven Instructions Selection and Application Scheduling in the DURASE system, ASAP '09: Proceedings of the 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors, pp.145-152, 2009.

K. Martin, C. Wolinski, K. Kuchcinski, and A. , Floc'h et F. Charot : Sélection automatique d'instructions et ordonnancement d'applications basés sur la programmation par contraintes, 13ème Symposium en Architecture de machines (Sym- pA'13), 2009.

C. Wolinski, K. Kuchcinski, K. Martin, E. Raffin, and F. Charot, How Constraints Programming Can Help You in the Generation of Optimized Application Specific Reconfigurable Processor Extensions, International Conference on Engineering of Reconfigurable Systems & Algorithms Las VegasÉtats Vegas´VegasÉtats-Unis d'Amérique, 2009.
URL : https://hal.archives-ouvertes.fr/inria-00449775

. Workshops, . Démonstrations, ]. K. Posters, C. Kuchcinski, K. Wolinski et al., Charot et A. Floc'h : Identification and Selection of Embedded Processor Extensions, 16th International Conference on Principles and Practices of Constraint Programming, 2010.

K. Martin and F. Charot, Utilisation combinée d'approches statique et dynamique pour la génération d'instructions spécialisées, 2008.

K. Martin, C. Wolinski, K. Kuchcinski, and F. , Charot et A. Floc'h : Design of Processor Accelerators with Constraints, SweConsNet Workshop, 2009.

K. Martin, C. Wolinski, K. Kuchcinski, and F. , Charot et A. Floc'h : DURASE : Generic environment for Design and Utilization of Reconfigurable Application- Specific Processors Extensions, 2009.

K. Martin, C. Wolinski, K. Kuchcinski, F. Charot, and A. , Floc'h : Extraction automatique d'instructions spécialisées en utilisant la programmation par contraintes . GDR SoCSiP Laarhoven : Statistical cooling : A general approach to combinatorial optimization problems, Philips J. Res, vol.10, issue.404, pp.193-226, 1985.

A. V. Aho, M. Ganapathi, and S. W. , Code generation using tree matching and dynamic programming, ACM Transactions on Programming Languages and Systems, vol.11, issue.4, pp.491-516, 1989.
DOI : 10.1145/69558.75700

A. V. Aho, R. Sethi, and J. D. , Ullman : Compilers : principles, techniques, and tools, 1986.

C. Alippi, W. Fornaciari, L. Pozzi, and M. Sami, A DAG-based design approach for reconfigurable VLIW processors, Proceedings of the conference on Design, automation and test in Europe , DATE '99, p.57, 1999.
DOI : 10.1145/307418.307504

. Altera, NiosII Core Implementation Details

. Altera, NiosII Custom Instruction User Guide

K. K. Andrew-mihal and S. Weber, Customizable Embedded Processors : Design Technologies and Applications, 2006.

J. M. Arnold, D. A. Buell, and E. G. , Davis : Splash 2, SPAA '92: Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures, pp.316-322, 1992.
DOI : 10.1145/140901.141896

M. Arnold, Instruction Set Extension for Embedded Processors, Thèse de doctorat, 2001.

M. Arnold and H. Corporaal, Designing domain-specific processors. Hardware/Software Codesign, Proceedings of the Ninth International Symposium on, pp.61-66, 2001.

N. Arora, K. Chandramohan, N. Pothineni, and A. Kumar, Instruction Selection in ASIP Synthesis Using Functional Matching, 2010 23rd International Conference on VLSI Design, pp.146-151, 2010.
DOI : 10.1109/VLSI.Design.2010.68

K. Atasu, Hardware/Software partitioning for custom instruction processors, Thèse de doctorat, 2007.

K. Atasu, G. Dündar, and C. Ozturan, An integer linear programming approach for identifying instruction-set extensions, Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '05, pp.172-177, 2005.
DOI : 10.1145/1084834.1084880

K. Atasu, O. Mencer, W. Luk, and C. Ozturan, Dundar : Fast custom instruction identification by convex subgraph enumeration, Application-Specific Systems, Architectures and Processors ASAP 2008. International Conference on, pp.1-6, 2008.

K. Atasu, L. Pozzi, and P. Ienne, Automatic application-specific instruction-set extensions under microarchitectural constraints, DAC '03: Proceedings of the 40th conference on Design automation, 2003.

P. M. Athanas and H. F. Silverman, Processor reconfiguration through instruction-set metamorphosis, Computer, vol.26, issue.3, pp.11-18, 1993.
DOI : 10.1109/2.204677

B. Design and T. Inc, Evaluating DSP processor performance, 2002.

A. Bhattacharya, A. Konar, S. Das, C. Grosan, and A. Abraham, Hardware Software Partitioning Problem in Embedded System Design Using Particle Swarm Optimization Algorithm, 2008 International Conference on Complex, Intelligent and Software Intensive Systems, pp.171-176, 2008.
DOI : 10.1109/CISIS.2008.5

J. Bier, Use a Microprocessor, a DSP, or Both? Embedded Systems Conference, 2008.

N. N. B-`-inh, M. Imai, A. Shiomi, and N. Hikichi, A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts, DAC '96: Proceedings of the 33rd annual Design Automation Conference, pp.527-532, 1996.

P. Biswas, S. Banerjee, N. Dutt, P. Ienne, and L. Pozzi, Performance and energy benefits of instruction set extensions in an FPGA soft core. VLSI Design, Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on, p.6, 2006.

P. Biswas, S. Banerjee, N. Dutt, L. Pozzi, and P. Ienne, ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, Design, Automation and Test in Europe, pp.1246-1251, 2005.
DOI : 10.1109/DATE.2005.191

URL : https://hal.archives-ouvertes.fr/hal-00181685

P. Biswas, V. Choudhary, K. Atasu, L. Pozzi, P. Ienne et al., Introduction of local memory elements in instruction set extensions, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.729-734, 2004.
DOI : 10.1145/996566.996765

D. C. Black and J. Donovan, SystemC : From the Ground Up, 2005.

P. Bonzini, D. Harmanci, and L. Pozzi, A Study of Energy Saving in Customizable Processors, Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.304-312, 2007.
DOI : 10.1007/978-3-540-73625-7_32

P. Bonzini and L. Pozzi, Code transformation strategies for extensible embedded processors, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems , CASES '06, pp.242-252, 2006.
DOI : 10.1145/1176760.1176791

P. Bonzini and L. Pozzi, A Retargetable Framework for Automated Discovery of Custom Instructions, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP), pp.334-341, 2007.
DOI : 10.1109/ASAP.2007.4430002

P. Bonzini and L. Pozzi, Polynomial-Time Subgraph Enumeration for Automated Instruction Set Extension, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1331-1336, 2007.
DOI : 10.1109/DATE.2007.364482

P. Bonzini and L. Pozzi, On the Complexity of Enumeration and Scheduling for Extensible Embedded Processors. Rap. tech, 2008.

U. Bordoloi, H. P. Huynh, S. Chakraborty, and T. Mitra, Evaluating design trade-offs in customizable processors, Proceedings of the 46th Annual Design Automation Conference on ZZZ, DAC '09, pp.244-249, 2009.
DOI : 10.1145/1629911.1629978

E. Borin, F. Klein, N. Moreano, R. Azevedo, and G. Araujo, Fast instruction set customization. Embedded Systems for Real-Time Multimedia, pp.53-58, 2004.

F. Bouchez, A. Darte, C. Guillon, and F. Rastello, Register Allocation: What Does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How, LCPC'06: Proceedings of the 19th international conference on Languages and compilers for parallel computing, pp.283-298, 2007.
DOI : 10.1007/978-3-540-72521-3_21

P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh, Instruction generation and regularity extraction for reconfigurable processors, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '02, pp.262-269, 2002.
DOI : 10.1145/581630.581672

P. Brisk, A. Kaplan, and M. Sarrafzadeh, Area-efficient instruction set synthesis for reconfigurable system-on-chip designs, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.395-400, 2004.
DOI : 10.1145/996566.996679

J. M. Cardoso and P. C. , Diniz : Compilation Techniques for Reconfigurable Architectures, 2008.

V. Cern´ycern´y, Thermodynamical approach to the traveling salesman problem: An efficient simulation algorithm, Journal of Optimization Theory and Applications, vol.21, issue.1, pp.41-51, 1985.
DOI : 10.1007/BF00940812

G. Chaitin, Register allocation and spilling via graph coloring, ACM SIGPLAN Notices, vol.39, issue.4, pp.66-74, 2004.
DOI : 10.1145/989393.989403

N. Cheung, S. Parameswaran, and J. Henkel, INSIDE : INstruction Selection/Identification & Design Exploration for Extensible Processors, ICCAD '03

N. Cheung, S. Parameswarani, and J. , Henkel : A quantitative study and estimation models for extensible instructions in embedded processors, ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, pp.183-189, 2004.

H. Choi, J. Kim, C. Yoon, I. Park, S. H. Hwang et al., Synthesis of application specific instructions for embedded DSP software, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design , ICCAD '98, pp.603-614, 1999.
DOI : 10.1145/288548.289109

H. Choi, J. H. Yi, J. Lee, I. Park, and C. Kyung, Exploiting intellectual properties in ASIP designs for embedded DSP software, Proceedings of the 36th ACM/IEEE conference on Design automation conference , DAC '99, pp.939-944, 1999.
DOI : 10.1145/309847.310103

N. Clark, H. Zhong, and S. Mahlke, Processor acceleration through automated instruction set customization, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), pp.129-140, 2003.
DOI : 10.1109/MICRO.2003.1253189

N. Clark, H. Zhong, W. Tang, and S. Mahlke, Automatic Design of Application Specific Instruction Set Extensions Through Dataflow Graph Exploration, International Journal of Parallel Programming, vol.31, issue.6, pp.31429-449, 2003.
DOI : 10.1023/B:IJPP.0000004509.87424.3a

N. T. Clark, Customizing the computation capabilities of microprocessors, Thèse de doctorat

N. T. Clark, H. Zhong, and S. A. Mahlke, Automated Custom Instruction Generation for Domain-Specific Processor Acceleration, IEEE Transactions on Computers, vol.54, issue.10, pp.1258-1270, 2005.
DOI : 10.1109/TC.2005.156

J. Cong, Y. Fan, G. Han, A. Jagannathan, G. Reinman et al., Instruction set extension with shadow registers for configurable processors, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.99-106, 2005.
DOI : 10.1145/1046192.1046206

J. Cong, Y. Fan, G. Han, and Z. Zhang, Application-specific instruction generation for configurable processor architectures, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays , FPGA '04, pp.183-189, 2004.
DOI : 10.1145/968280.968307

M. Corazao, M. Khalaf, L. Guerra, and M. Potkonjak, Rabaey : Performance optimization using template mapping for datapath-intensive high-level synthesis . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, issue.8, pp.15877-888, 1996.

T. H. Cormen, C. E. Leiserson, R. L. Rivest, and C. Stein, Introduction to Algorithms, 2001.

R. Cytron, J. Ferrante, B. K. Rosen, M. N. Wegman, F. K. Zadeck et al., An efficient method of computing static single assignment form CUSTARD -a customisable threaded FPGA soft processor and tools, POPL '89: Proceedings of the 16th ACM SIGPLAN-SIGACT symposium on Principles of programming languages Field Programmable Logic and Applications, 2005. International Conference on, pp.25-35, 1989.

B. K. Dwivedi, A. Kejariwal, M. Balakrishnan, and A. Kumar, Rapid Resource-Constrained Hardware Performance Estimation, Seventeenth IEEE International Workshop on Rapid System Prototyping (RSP'06), pp.40-46, 2006.
DOI : 10.1109/RSP.2006.33

A. Fauth, J. Van-praet, and M. Freericks, Describing instruction set processors using nML, Proceedings the European Design and Test Conference. ED&TC 1995, p.503, 1995.
DOI : 10.1109/EDTC.1995.470354

Y. Fei, S. Ravi, A. Raghunathan, and N. K. , Jha : Energy Estimation for Extensible Processors, DATE '03: Proceedings of the conference on Design, Automation and Test in Europe, p.10682, 2003.

T. A. Feo and M. G. , Greedy Randomized Adaptive Search Procedures, Journal of Global Optimization, vol.68, issue.2, pp.109-133, 1995.
DOI : 10.1007/BF01096763

F. Magno and Q. Pereira, Register Allocation by Puzzle Solving, Thèse de doctorat, 2008.

J. A. Fisher, P. Faraboschi, and C. Young, Embedded Computing : A VLIW Approach to Architecture, Compilers and Tools, 2004.

M. Flynn, Some Computer Organizations and Their Effectiveness, IEEE Transactions on Computers, vol.21, issue.9, pp.948-960, 1972.
DOI : 10.1109/TC.1972.5009071

C. W. Fraser, R. R. Henry, and T. A. , BURG, ACM SIGPLAN Notices, vol.27, issue.4, pp.68-76, 1992.
DOI : 10.1145/131080.131089

T. Fruewirth and S. Abdennadher, Essentials of Constraint Programming, 2003.
DOI : 10.1007/978-3-662-05138-2

D. D. Gajski, N. D. Dutt, A. C. Wu, and S. Y. Lin, High-level synthesis : introduction to chip and system design, 1992.
DOI : 10.1007/978-1-4615-3636-9

C. Galuzzi, Automatically Fused Instructions, Thèse de doctorat, 2009.

C. Galuzzi and K. Bertels, The Instruction-Set Extension Problem, ARC '08: Proceedings of the 4th international workshop on Reconfigurable Computing, pp.209-220, 2008.
DOI : 10.1145/1968502.1968509

C. Galuzzi and K. Bertels, Vassiliadis : A Linear Complexity Algorithm for the Generation of multiple Input Single Output Instructions of Variable Size, SAMOS, pp.283-293, 2007.

C. Galuzzi, K. Bertels, and S. Vassiliadis, The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions, 2007 International Conference on Field-Programmable Technology, pp.337-340, 2007.
DOI : 10.1109/FPT.2007.4439280

C. Galuzzi, E. M. Panainte, Y. Yankova, K. Bertels, and S. Vassiliadis, Automatic selection of application-specific instruction-set extensions, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis , CODES+ISSS '06, pp.160-165, 2006.
DOI : 10.1145/1176254.1176293

C. Galuzzi, D. Theodoropoulos, and R. Meeuws, Bertels : Algorithms for the automatic extension of an instruction-set, DATE, pp.548-553, 2009.

M. R. Garey and D. S. Johnson, Computers and Intractability; A Guide to the Theory of NP-Completeness, 1990.

. Gecos, Generic compiler suite

W. Geurts, Accelerator Data-Path Synthesis for High-Throughput Signal Processing Applications, 1997.
DOI : 10.1007/978-1-4419-8720-4

T. Glokler, S. Bitterlich, and H. Meyr, ICORE: a low-power application specific instruction set processor for DVB-T acquisition and tracking, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541), pp.102-106, 2000.
DOI : 10.1109/ASIC.2000.880684

R. Gonzalez, Xtensa: a configurable and extensible processor, IEEE Micro, vol.20, issue.2, pp.60-70, 2000.
DOI : 10.1109/40.848473

M. Gries and K. Keutzer, Building ASIPs: The Mescal Methodology, 2005.
DOI : 10.1007/b136892

Y. Guo, G. J. Smit, H. Broersma, and P. M. , Heysters : A graph covering algorithm for a coarse grain reconfigurable system, LCTES '03: Proceedings of the 2003 ACM SIGPLAN conference on Language, compiler, and tool for embedded systems, 2003.

M. R. Guthaus, J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge et al., MiBench: A free, commercially representative embedded benchmark suite, Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538), pp.3-14, 2001.
DOI : 10.1109/WWC.2001.990739

G. Hadjiyiannis, S. Hanono, and S. Devadas, ISDL, Proceedings of the 34th annual conference on Design automation conference , DAC '97, pp.299-302, 1997.
DOI : 10.1145/266021.266108

A. Halambi, P. Grun, V. Ganesh, A. Khare, and N. Dutt, Nicolau : EX- PRESSION : A Language for Architecture Exploration through Compiler/Simulator Retargetability, Europe Conference and Exhibition, p.485, 1999.

R. W. Hartenstein, J. Becker, R. Kress, H. S. Hauck, T. Fry et al., Reinig : High-performance computing using a reconfigurable accelerator. Concurrency -Practice and Experience, The Chimaera reconfigurable functional unit. Very Large Scale Integration (VLSI) Systems, pp.429-443, 1996.

J. Hauser and J. Wawrzynek, Garp: a MIPS processor with a reconfigurable coprocessor, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186), pp.12-21, 1997.
DOI : 10.1109/FPGA.1997.624600

J. Hidalgo and J. , Lanchares : Functional Partitioning for Hardware-Software Codesign using Genetic Algorithms, EUROMICRO Conference, p.631, 1997.

A. Hoffmann, H. Meyr, and R. Leupers, Architecture Exploration for Embedded Processors with Lisa, 2002.
DOI : 10.1007/978-1-4757-4538-2

A. Hoffmann, A. Nohl, S. Pees, G. Braun, and H. Meyr, Generating production quality software development tools using a machine description language, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.674-678, 2001.
DOI : 10.1109/DATE.2001.915097

A. Hoffmann, O. Schliebusch, A. Nohl, G. Braun, O. Wahlen et al., A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281), pp.625-630, 2001.
DOI : 10.1109/ICCAD.2001.968726

I. Huang and A. M. , Despain : Synthesis of instruction sets for pipelined microprocessors, DAC '94: Proceedings of the 31st annual Design Automation Conference, pp.5-11, 1994.

Z. Huang, S. Malik, N. Moreano, and G. Araujo, The design of dynamically reconfigurable datapath coprocessors, ACM Transactions on Embedded Computing Systems, vol.3, issue.2, pp.361-384, 2004.
DOI : 10.1145/993396.993403

H. P. Huynh and T. Mitra, Runtime Adaptive Extensible Embedded Processors ??? A Survey, SAMOS '09: Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation, pp.215-225, 2009.
DOI : 10.1007/978-3-642-03138-0_23

Y. Hwang, J. Chen, and J. Chiu, HW/SW Auto-Coupling for Fast IP Integration in SoC Designs. Embedded Software and Systems, Second International Conference on, pp.556-563, 2008.

C. Iseli and E. Sanchez, Spyder: A SURE (SUperscalar and REconfigurable) processor, The Journal of Supercomputing, vol.22, issue.7, pp.231-252, 1995.
DOI : 10.1007/BF01212870

. Jacop, JaCoP Library User's Guide

M. K. Jain, M. Balakrishnan, and A. Kumar, ASIP design methodologies: survey and issues, VLSI Design 2001. Fourteenth International Conference on VLSI Design, p.76, 2001.
DOI : 10.1109/ICVD.2001.902643

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.19.1875

M. K. Jain, M. Balakrishnan, and A. Kumar, An efficient technique for exploring register file size in ASIP synthesis, Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems , CASES '02, pp.252-261, 2002.
DOI : 10.1145/581630.581671

R. Jayaseelan, H. Liu, and T. Mitra, Exploiting forwarding to improve data bandwidth of instruction-set extensions, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.43-48, 2006.
DOI : 10.1145/1146909.1146924

A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, and J. Foster, An FPGA-based VLIW processor with custom hardware execution, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, pp.107-117, 2005.
DOI : 10.1145/1046192.1046207

R. M. Karp, R. E. Miller, and J. W. Thatcher, Reducibility Among Combinatorial Problems, Complexity of Computer Computations, pp.85-103, 1972.

K. Karuri, M. A. Faruque, S. Kraemer, R. Leupers, and G. Ascheid, Meyr : Fine-grained application source code profiling for ASIP design, DAC '05: Proceedings of the 42nd annual Design Automation Conference, pp.329-334, 2005.

R. Kastner, S. Ogrenci-memik, and E. Bozorgzadeh, Sarrafzadeh : Instruction Generation for Hybrid Reconfigurable Systems, ICCAD, p.127, 2001.

B. Kastrup, Automatic Synthesis of Reconfigurable Instruction Set Accelerators, Thèse de doctorat, 2001.

B. Kastrup, A. Bink, and J. Hoogerbrugge, ConCISe: a compiler-driven CPLD-based instruction set accelerator, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375), p.92, 1999.
DOI : 10.1109/FPGA.1999.803671

B. W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs. The Bell system technical journal, pp.291-307, 1970.

J. Kin, C. Lee, and W. H. Mangione-smith, Potkonjak : Power Efficient Mediaprocessors : Design Space Exploration, Design Automation Conference, pp.321-326, 1999.
DOI : 10.1109/dac.1999.781334

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.16.575

S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, Science, vol.220, issue.4598, pp.671-680, 1983.
DOI : 10.1126/science.220.4598.671

I. Kuon and J. Rose, Measuring the gap between FPGAs and ASICs, FPGA '06: Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays, pp.21-30, 2006.

F. J. Kurdahi and A. C. Parker, REAL: a program for REgister ALlocation, 24th ACM/IEEE conference proceedings on Design automation conference , DAC '87, pp.210-215, 1987.
DOI : 10.1145/37888.37920

S. Lam and T. Srikanthan, Rapid design of area-efficient custom instructions for reconfigurable embedded processing, Journal of Systems Architecture, vol.55, issue.1, pp.1-14, 2009.
DOI : 10.1016/j.sysarc.2008.06.003

J. Larrosa, Valiente : Constraint satisfaction algorithms for graph pattern matching, Mathematical Structures in Computer Science, vol.12, pp.403-422, 2002.

C. Lee, M. Potkonjak, and W. H. Mangione-smith, MediaBench : A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems, International Symposium on Microarchitecture, pp.330-335, 1997.

R. Leupers, Retargetable Code Generation for Digital Signal Processors, 1997.
DOI : 10.1007/978-1-4757-2570-4

R. Leupers, Code selection for media processors with SIMD instructions, Europe Conference and Exhibition 2000. Proceedings, pp.4-8, 2000.

R. Leupers, K. Karuri, S. Kraemer, and M. Pandey, A design flow for configurable embedded processors based on optimized instruction set extension synthesis, Proceedings of the Design Automation & Test in Europe Conference, pp.581-586, 2006.
DOI : 10.1109/DATE.2006.243972

R. Leupers and P. Marwedel, Retargetable generation of code selectors from HDL processor models, Proceedings European Design and Test Conference. ED & TC 97, p.140, 1997.
DOI : 10.1109/EDTC.1997.582348

R. Leupers and P. Marwedel, Retargetable compiler technology for embedded systems : tools and applications, 2001.
DOI : 10.1007/978-1-4757-6420-8

R. L. Leupers and S. Bashford, Graph-based code selection techniques for embedded processors, ACM Transactions on Design Automation of Electronic Systems, vol.5, issue.4, pp.794-814, 2000.
DOI : 10.1145/362652.362661

S. Liao, S. Devadas, K. Keutzer, and S. Tjiang, Instruction selection using binate covering for code size optimization, ICCAD '95: Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, pp.393-399, 1995.

C. Liem, T. May, and P. Paulin, Instruction-set matching and selection for DSP and ASIP code generation The European Event in ASIC Design, European Design and Test Conference The European Conference on Design Automation Proceedings., p, pp.31-37, 1994.

H. Lin and Y. Fei, Utilizing custom registers in application-specific instruction set processors for register spills elimination, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, pp.323-328, 2007.
DOI : 10.1145/1228784.1228863

H. Lin and Y. Fei, Resource sharing of pipelined custom hardware extension for energy-efficient application-specific instruction set processor design, Computer Design ICCD 2009. IEEE International Conference on, pp.158-165, 2009.

Y. Lü, L. Shen, L. Huang, Z. Wang, and N. Xiao, Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques, DAC '08: Proceedings of the 45th annual Design Automation Conference, pp.197-200, 2008.

P. Marwedel, D. Lanneer, J. V. Praet, A. Kifli, K. Schoofs et al., CHESS : Retargetable Code Generation For Embedded DSP Processors, pp.85-102, 1995.

M. M. Mbaye, N. Bélanger, Y. Savaria, and S. Pierre, A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration, The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, vol.25, issue.7, pp.297-315, 2007.
DOI : 10.1007/s11265-007-0050-0

B. D. Mckay, The nauty page, 2004.

B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix, Field-Programmable Logic and Applications, pp.61-70, 2003.
DOI : 10.1007/978-3-540-45234-8_7

A. J. Menezes, S. A. Vanstone, and P. C. , Oorschot : Handbook of Applied Cryptography, 1996.

V. Messé, Production de compilateurs flexibles pour la conception de processeurs programmables spécialisés, Thèse de doctorat, 1999.

H. Meyr, System-on-chip for communications: the dawn of ASIPs and the dusk of ASICs, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682), pp.4-5, 2003.
DOI : 10.1109/SIPS.2003.1235634

T. Miyamori, Olukotun : A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, Programmable Custom Computing Machines, Annual IEEE Symposium on, 1998.

L. Moll, J. Vuillemin, and P. Boucard, High-energy physics on DECPeRLe-1 programmable active memory, FPGA '95: Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays, pp.47-52, 1995.

G. E. Moore, N. Moreano, E. Borin, C. De-souza, and G. Araujo, Cramming More Components onto Integrated Circuits Efficient datapath merging for partially reconfigurable architectures. Computer-Aided Design of Integrated Circuits and Systems, Electronics IEEE Transactions, vol.38159, issue.87, pp.114-117, 1965.

B. Moret and H. D. Shapiro, Algorithms from P to NP, 1991.

S. S. Muchnick, Advanced compiler design and implementation, 1997.

L. P. Cordella, P. Foggia, and C. Sansone, A (sub)graph isomorphism algorithm for matching large graphs, IEEE Transactions on Pattern Analysis and Machine Intelligence, vol.26, issue.10, pp.1367-1372, 2004.
DOI : 10.1109/TPAMI.2004.75

D. A. Patterson and J. L. Hennessy, Computer Architecture, ACM Turing Centenary Celebration on, ACM-TURING '12, 1990.
DOI : 10.1145/2322176.2322187

A. Peymandoust, L. Pozzi, P. Ienne, and G. D. Micheli, Automatic Instruction Set Extension and Utilization for Embedded Processors. Application-Specific Systems, Architectures and Processors, IEEE International Conference on, p.108, 2003.

. Polarssl, Small cryptographic library

N. Pothineni, A. Kumar, and K. Paul, Application Specific Datapath Extension with Distributed I/O Functional Units, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07), pp.551-558, 2007.
DOI : 10.1109/VLSID.2007.40

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.73.8213

N. Pothineni, A. Kumar, and K. Paul, Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors, 21st International Conference on VLSI Design (VLSID 2008), pp.261-266, 2008.
DOI : 10.1109/VLSI.2008.93

L. Pozzi, Methodologies for the Design of Application Specific Reconfigurable VLIW Processors, Thèse de doctorat, 2000.

L. Pozzi, K. Atasu, and P. Ienne, Exact and approximate algorithms for the extension of embedded processor instruction sets. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.25, issue.7, pp.1209-1229, 2006.

L. Pozzi and P. Ienne, Exploiting pipelining to relax register-file port constraints of instruction-set extensions, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems , CASES '05, pp.2-10, 2005.
DOI : 10.1145/1086297.1086300

M. Purnaprajna, M. Reformat, and W. Pedrycz, Genetic algorithms for hardware???software partitioning and optimal resource allocation, Journal of Systems Architecture, vol.53, issue.7, pp.339-354, 2007.
DOI : 10.1016/j.sysarc.2006.10.012

B. Radunovic and V. M. , Milutinovic : A Survey of Reconfigurable Computing Architectures, FPL '98: Proceedings of the 8th International Workshop on Field- Programmable Logic and Applications, From FPGAs to Computing Paradigm, pp.376-385, 1998.

D. S. Rao and F. J. Kurdahi, Partitioning by regularity extraction, [1992] Proceedings 29th ACM/IEEE Design Automation Conference, pp.235-238, 1992.
DOI : 10.1109/DAC.1992.227830

R. Razdan, K. Brace, and M. Smith, PRISC software acceleration techniques, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.145-149, 1994.
DOI : 10.1109/ICCD.1994.331875

R. Razdan and M. D. , Smith : A high-performance microarchitecture with hardwareprogrammable functional units, MICRO 27: Proceedings of the 27th annual international symposium on Microarchitecture, pp.172-180, 1994.

S. Rixner, W. Dally, B. Khailany, P. Mattson, U. Kapasi et al., Register organization for media processing, Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550), pp.375-386, 2000.
DOI : 10.1109/HPCA.2000.824366

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.34.7602

F. Rossi, P. V. Beek, and T. Walsh, Handbook of Constraint Programming (Foundations of Artificial Intelligence), 2006.

C. R. Rupp, M. Landguth, T. Garverick, E. Gomersall, H. Holt et al., Gokhale : The NAPA Adaptive Processing Architecture, FCCM '98: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, p.28, 1998.

H. Singh, M. Lee, G. Lu, F. Kurdahi, N. Bagherzadeh et al., MorphoSys, Proceedings of the 37th conference on Design automation , DAC '00, pp.465-481, 2000.
DOI : 10.1145/337292.337583

. Soclib, Open platform for virtual prototyping of multi-processors system on chip (MP-SoC)

S. Sorlin, Mesurer la similarité de graphes, Thèse de doctorat en informatique, 2006.

S. Sorlin and C. , Solnon : A global constraint for graph isomorphism problems. Lecture notes in computer science ISSN 0302-9743, pp.287-301, 2004.

F. Sun, S. Ravi, A. Raghunathan, and N. K. , Jha : Synthesis of custom processors based on extensible platforms, ICCAD '02: Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, pp.641-648, 2002.

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, A Scalable Application- Specific Processor Synthesis Methodology, ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.283, 2003.

. Tensilica, Texas Instrument Ullmann : An Algorithm for Subgraph Isomorphism, J. ACM, vol.23, issue.1, pp.31-42, 1976.

F. Vahid and T. D. Le, Extending the Kernighan/Lin Heuristic for Hardware and Software Functional Partitioning. Design Automation for Embedded Systems, pp.237-261, 1997.

S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov et al., The MOLEN polymorphic processor, IEEE Transactions on Computers, vol.53, issue.11, pp.1363-1375, 2004.
DOI : 10.1109/TC.2004.104

B. Veale, J. Antonio, M. Tull, and S. Jones, Selection of instruction set extensions for an FPGA embedded processor core. Parallel and Distributed Processing Symposium, IPDPS, 2006.

A. Verma and P. Brisk, Lenne : Fast, quasi-optimal, and pipelined instruction-set extensions, Design Automation Conference, pp.334-339, 2008.

A. K. Verma, P. Brisk, and P. Ienne, Rethinking custom ISE identification, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems , CASES '07, pp.125-134, 2007.
DOI : 10.1145/1289881.1289905

A. K. Verma and P. Brisk, Ienne : Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.29, issue.3, pp.341-354, 2010.

E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee et al., Baring it all to software: Raw machines, Computer, vol.30, issue.9, pp.3086-93, 1997.
DOI : 10.1109/2.612254

URL : http://cag.lcs.mit.edu/commit/papers/97/raw-TR.pdf

G. Wang, W. Gong, and R. Kastner, System Level Partitioning for Programmable Platforms Using the Ant Colony Optimization, International Workshop on Logic & Synthesis (IWLS'04), 2004.

T. Wiangtong, P. Y. Cheung, and W. Luk, Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware/Software Codesign. Design Automation for Embedded Systems, pp.425-449, 2002.

M. Wirthlin, Hutchings : A Dynamic Instruction Set Computer, Programmable Custom Computing Machines, Annual IEEE Symposium on, p.99, 1995.

R. Wittig and P. Chow, OneChip: an FPGA processor with reconfigurable logic, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines FPGA-96, pp.126-135, 1996.
DOI : 10.1109/FPGA.1996.564773

C. Wolinski and K. Kuchcinski, Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP), pp.328-333, 2007.
DOI : 10.1109/ASAP.2007.4430001

C. Wolinski and K. Kuchcinski, Automatic selection of application-specific reconfigurable processor extensions, DATE '08: Proceedings of the conference on Design, automation and test in Europe, pp.1214-1219, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00451683

C. Wolinski, K. Kuchcinski, and A. Postula, UPaK : Abstract Unified Pattern Based Synthesis Kernel for Hardware and Software Systems, DATE U-Booth, 2007.

C. Wolinski, K. Kuchcinski, and E. Raffin, Automatic design of application-specific reconfigurable processor extensions with UPaK synthesis kernel, ACM Transactions on Design Automation of Electronic Systems, vol.15, issue.1, pp.1-36, 2009.
DOI : 10.1145/1640457.1640458

URL : https://hal.archives-ouvertes.fr/inria-00451649

C. Wolinski, K. Kuchcinski, E. Raffin, and F. Charot, Architecture-Driven Synthesis of Reconfigurable Cells, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, pp.531-538, 2009.
DOI : 10.1109/DSD.2009.183

URL : https://hal.archives-ouvertes.fr/inria-00449757

C. Wolinski, K. Kuchcinski, and J. Teich, Hannig : Optimization of Routing and Reconfiguration Overhead, Programmable Processor Array Architectures. Field-Programmable Custom Computing Machines, Annual IEEE Symposium on, pp.306-309, 2008.

Z. A. Ye, A. Moshovos, S. Hauck, and P. Banerjee, CHIMAERA : a highperformance architecture with a tightly-coupled reconfigurable functional unit, pp.225-235, 2000.

A. Yeung and J. Rabaey, A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms, [1993] Proceedings of the Twenty-sixth Hawaii International Conference on System Sciences, pp.169-178, 1993.
DOI : 10.1109/HICSS.1993.270747

P. Yiannacouras, J. G. Steffan, and J. Rose, Application-specific customization of soft processor microarchitecture, Proceedings of the internation symposium on Field programmable gate arrays , FPGA'06, pp.201-210, 2006.
DOI : 10.1145/1117201.1117231

P. Yu and T. Mitra, Characterizing embedded applications for instruction-set extensible processors, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.723-728, 2004.
DOI : 10.1145/996566.996764

P. Yu and T. Mitra, Scalable custom instructions identification for instruction-set extensible processors, Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems , CASES '04, pp.69-78, 2004.
DOI : 10.1145/1023833.1023844

P. Yu and T. Mitra, Disjoint Pattern Enumeration for Custom Instructions Identification, 2007 International Conference on Field Programmable Logic and Applications, pp.273-278, 2007.
DOI : 10.1109/FPL.2007.4380659

K. Zhao, J. Bian, S. Dong, Y. Song, and S. Goto, Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration, 9th International Symposium on Quality Electronic Design (isqed 2008)
DOI : 10.1109/ISQED.2008.4479748