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Génération automatique d'extensions de jeux d'instructions de processeurs

Kevin Martin 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
Abstract : ASIPs (Application Specific Instruction set Processors) are custom processors that offer a good trade-off between performance and flexibility. A common processor customization approach is to augment its standard instruction set with application-specific instructions that are implemented on specifically designed hardware extensions (reconfigurable cells). These extensions are often directly connected to the processor's data-path. The design of the ASIP processor must rely on dedicated methodologies and software tools that manage both the design constraints and the growing complexity of applications. In this context, the aims of this thesis were to propose a new methodology for the automatic generation of instruction-set extensions. In the first step of our proposed design flow, we generate the instruction candidates that satisfy some architectural and technological constraints. In the second step, we identify the set of standard and customized instructions that minimizes the sequential application's execution time. In the next step, optimized hardware extensions and the corresponding application program including new instructions are generated. During the hardware generation, the optimizations of the hardware resources such as registers and multiplexers are simultaneously carried out. In our proposed design flow we used the constraint-based approach to solve the computationally complex problems of instruction identification, instruction selection and register allocation.
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Submitted on : Wednesday, October 13, 2010 - 5:38:41 PM
Last modification on : Wednesday, December 18, 2019 - 5:19:39 PM
Document(s) archivé(s) le : Thursday, October 25, 2012 - 5:11:14 PM


  • HAL Id : tel-00526133, version 1


Kevin Martin. Génération automatique d'extensions de jeux d'instructions de processeurs. Génie logiciel [cs.SE]. Université Rennes 1, 2010. Français. ⟨tel-00526133⟩



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