E. Synchronous and . Figure, 5: An extract of Gaspard2 StateGraph, which is proposed according to the metamodel of UML state machines

M. Maroti, A. Ledeczi, and P. Volgyesi, The Generic Modeling Environment, Proceedings of the IEEE Workshop on Intelligent Signal Processing (WISP'01), p.61, 2001.

M. D. Adams, The JPEG-2000 still image compression standard, p.16, 2001.

N. Aizenbud-resher, R. F. Paige, J. Rubin, Y. Shalam-gafni, and D. S. Kolovos, Operational semantics for traceability, ECMDA Traceability Work-shop (ECMDA-TW) 2005, p.32, 2005.

A. Amar, P. Boulet, and P. Dumont, Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model, 8th International Symposium on Parallel Architectures,Algorithms and Networks (ISPAN'05), 2005.
DOI : 10.1109/ISPAN.2005.70

URL : https://hal.archives-ouvertes.fr/inria-00565167

C. André, Representation and Analysis of Reactive Behaviors: A Synchronous Approach, Computational Engineering in Systems Applications (CESA), pp.19-29, 1996.

C. André, SyncCharts: a Visual Representation of Reactive Behaviors, Research Report, vol.9656, issue.3, p.53, 1996.

C. André, Semantics of SSM (Safe State Machine)

L. Apvrille, W. Muhammad, R. Ameur-boulifa, S. Coudert, and R. Pacalet, A UMLbased Environment for System Design Space Exploration. Electronics, Circuits and Systems, ICECS '06. 13th IEEE International Conference on, pp.1272-1275, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00525101

L. Benini and G. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921

A. Benveniste, P. L. Guernic, and P. Aubry, Compositionality in Dataflow Synchronous Languages: Specification and Code Generation, volume LNCS 1536, page 61, Proceedings of the 1997 Workshop on Compositionality Albert Benveniste, p.78, 1997.

G. Berry, The constructive semantics of pure Esterel, p.63

G. Berry and G. Gonthier, The Esterel synchronous programming language: design, semantics, implementation, Science of Computer Programming, vol.19, issue.2, pp.87-152, 1992.
DOI : 10.1016/0167-6423(92)90005-V

URL : https://hal.archives-ouvertes.fr/inria-00075711

G. Berry and E. Sentovich, Multiclock Esterel, Proc. CHARME'2001, Correct Hardare Design and Verification Methods, p.62, 2001.
DOI : 10.1007/3-540-44798-9_10

L. Besnard, T. Gautier, and P. L. Guernic, Signal Reference Manual

L. Besnard, H. Marchand, and E. Rutten, The Sigali Tool Box Environment, 2006 8th International Workshop on Discrete Event Systems, p.59, 2006.
DOI : 10.1109/WODES.2006.382518

J. Bézivin, On the unification power of models, Software and System Modeling (SoSym), pp.171-188, 2005.
DOI : 10.1109/MS.2003.1231147

]. P. Boulet, Array-OL revisited, multidimensional intensive signal processing specification, pp.40-41, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00128840

P. Boulet, Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing, p.18, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00261178

F. Boussinot and R. De-simone, The Esterel language. another look at real time programming, Proceedings of the IEEE, pp.1293-1304, 1991.
URL : https://hal.archives-ouvertes.fr/inria-00075075

C. Brunette, J. Talpin, L. Besnard, and T. Gautier, Modeling multi-clocked dataflow programs using the Generic Modeling Environment, Synchronous Languages, Applications, and Programming, p.118, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00541310

J. Buck, S. Ha, E. Lee, and D. Messerschmitt, Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, Special issue on Simulation Software Development, pp.155-182, 1994.
DOI : 10.1016/B978-155860702-6/50048-X

P. Caspi, D. Pilaud, N. Halbwachs, and J. A. Plaice, LUSTRE: a declarative language for real-time programming, Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages , POPL '87, pp.178-188, 1987.
DOI : 10.1145/41625.41641

A. Charfi, A. Gamatié, A. Honoré, J. Dekeyser, and M. Abid, Validation de modèles dans un cadre d'IDM dédié à la conception de systémes sur puce, 4èmes Jounées sur l'Ingénierie Dirigée par les Modèles -IDM'08, p.167, 2008.

T. A. Claasen, System on a chip: changing ic design today and in the future, IEEE Micro, vol.23, issue.3, pp.20-26, 2003.
DOI : 10.1109/MM.2003.1209463

A. Cuccuru, Modélisation Unifiée des Aspects Répétitifs dans la Conception Conjointe Logicielle/Matérielle des Systèmes sur Puce à Hautes Performances, p.40, 2005.

K. Czarnecki and S. Helsen, Classification of model tranformation approaches, Proceeding of OOPSLA Workshop on Generative Techniques in the Context of Model Driven Architecture, p.31, 2003.

A. Demeure and Y. D. Gallo, An array approach for signal processing design, Sophia-Antipolis conference on Micro-Electronics (SAME'98), System-on-Chip Session, p.17, 1998.

A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J. Dufourd et al., Array-OL: Proposition d'un formalisme tableau pour le traitement de signal multidimensionnel, Colloque GRETSI sur le Traitement du Signal et de l'Image, p.40, 1995.

P. Dumont, Spécification multidimensionnelle pour le traitement du signal systématique, p.73, 2005.

P. Dumont and P. Boulet, Another multidimensional synchronous dataflow: Simulating Array-Ol in Ptolemy II, 2005.
URL : https://hal.archives-ouvertes.fr/inria-00070490

. Eclipse, Eclipse Modeling Framework, p.128

S. Edwards, L. Lavagno, E. A. Lee, and A. Sangiovanni-vincentelli, Design of embedded systems: formal models, validation, and synthesis, Proceedings of the IEEE, vol.85, issue.3, pp.366-390, 1997.
DOI : 10.1109/5.558710

A. Etien, C. Dumoulin, and E. Renaux, Towards a Unified Notation to Represent Model Transformation, Research Report, vol.6187, issue.31, p.125, 2007.
URL : https://hal.archives-ouvertes.fr/inria-00145204

M. Eva, SSADM Version 4: A User's Guide, p.27, 1994.

A. D. Falkoff and K. E. Iverson, The Design of APL, IBM Journal of Research and Development, vol.17, issue.4, pp.324-334, 1973.
DOI : 10.1147/rd.174.0324

J. Favre, J. Estublier, and M. , Blay-Fornarino, editors. L'ingénierie dirigée par les modèles , au-delà du MDA, Hermès Science, vol.26, p.27, 2006.

P. Feautrier, Some efficient solutions to the affine scheduling problem. I. One-dimensional time, International Journal of Parallel Programming, vol.40, issue.6, pp.313-348, 1992.
DOI : 10.1007/BF01407835

P. Feautrier, Some efficient solutions to the affine scheduling problem. Part II. Multidimensional time, International Journal of Parallel Programming, vol.2, issue.4, pp.389-420, 1992.
DOI : 10.1007/BF01379404

H. Fecher, J. Schönborn, M. Kyas, and W. P. De-roever, 29 New Unclarities in the Semantics of UML 2.0 State Machines, In ICFEM Lecture Notes in Computer Science, vol.3785, issue.37, pp.52-65, 2005.
DOI : 10.1007/11576280_5

D. D. Gajski and R. Kuhn, Guest Editors' Introduction: New VLSI Tools, Computer, vol.16, issue.12, pp.11-14, 1983.
DOI : 10.1109/MC.1983.1654264

A. Gamatié, E. Rutten, and H. Yu, A Model for the Mixed-Design of Data- Intensive and Control-Oriented Embedded Systems, p.110, 2008.

A. Gamatié, É. Rutten, H. Yu, P. Boulet, and J. Dekeyser, Modeling and Formal Validation of High-Performance Embedded Systems, 2008 International Symposium on Parallel and Distributed Computing, p.167, 2008.
DOI : 10.1109/ISPDC.2008.28

A. Gamatié, É. Rutten, H. Yu, P. Boulet, and J. Dekeyser, Synchronous Modeling and Analysis of Data Intensive Applications, EURASIP Journal on Embedded Systems, vol.2008, issue.1, p.180, 2008.
DOI : 10.1007/BF01379404

A. Girault and H. Yu, A flexible method to tolerate value sensor failures, 2006 IEEE Conference on Emerging Technologies and Factory Automation, p.175, 2006.
DOI : 10.1109/ETFA.2006.355435

C. Glitia and P. Boulet, High level loop transformations for multidimensional signal processing embedded applications, International Symposium on Systems, Architectures , MOdeling, and Simulation (SAMOS VIII), p.73, 2008.
URL : https://hal.archives-ouvertes.fr/inria-00565154

R. Goering, SoC value linked to software, EE Times, 2005.

M. Griebl, P. Faber, and C. Lengauer, Space???time mapping and tiling: a helpful combination, Concurrency and Computation: Practice and Experience, vol.16, issue.23, pp.221-246, 2004.
DOI : 10.1002/cpe.772

N. Halbwachs, Synchronous programming of reactive systems, Kluwer Academic Pub, vol.50, p.51, 1993.

N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud, The synchronous dataflow programming language Lustre, Proceedings of the IEEE, p.56, 1991.

N. Halbwachs, F. Lagnier, and P. Raymond, Synchronous Observers and the Verification of Reactive Systems, Third Int. Conf. on Algebraic Methodology and Software Technology, AMAST'93 Workshops in Computing, p.57, 1993.
DOI : 10.1007/978-1-4471-3227-1_8

N. Halbwachs and D. Pilaud, Use of a real-time declarative language for systolic array design and simulation, International Workshop on Systolic Arrays, p.57, 1986.

N. Halbwachs and M. Péron, Discovering properties about arrays in simple programs, PLDI, 1957.
URL : https://hal.archives-ouvertes.fr/hal-00288274

D. Harel, H. Lachover, A. Naamad, A. Pnueli, M. Politi et al., STATEMATE: a working environment for the development of complex reactive systems, IEEE Transactions on Software Engineering, vol.16, issue.4, pp.403-414, 1990.
DOI : 10.1109/32.54292

D. Harel and A. Naamad, The STATEMATE semantics of statecharts, ACM Transactions on Software Engineering and Methodology, vol.5, issue.4, pp.293-333, 1996.
DOI : 10.1145/235321.235322

D. Harel and A. Pnueli, On the Development of Reactive Systems, pp.477-498, 1985.
DOI : 10.1007/978-3-642-82453-1_17

F. High-performance and . Forum, High performance fortran language specification, p.76, 1997.

. Inria-dart and . Project, Gaspard2. https://gforge.inria.fr/projects/gaspard2, p.40

G. Kahn, The semantics of simple language for parallel programming, IFIP Congress of Information Processing, pp.471-475, 1974.

G. Kiczales, J. Lamping, A. Menhdhekar, C. Maeda, C. Lopes et al., Aspect-oriented programming, Proceedings European Conference on Object-Oriented Programming, pp.220-247, 1997.

A. Kountouris and P. L. Guernic, Profiling of SIGNAL programs and its application in the timing evaluation of design implementations, IEE Colloquium on Hardware-Software Cosynthesis for Reconfigurable Systems, pp.6-7, 1996.
DOI : 10.1049/ic:19960225

URL : https://hal.archives-ouvertes.fr/hal-00544253

O. Labbani, Modélisation à haut niveau du contrôle dans des applications de traitement systématique à parallélisme massif, pp.96-97, 2006.

O. Labbani, J. Dekeyser, P. Boulet, and E. Rutten, Introducing control in the Gas- pard2 data-parallel metamodel: Synchronous approach, Int'l Workshop on Modeling and Analysis of Real-Time and Embedded Systems (MARTES'05), p.97, 2005.

D. Latella, I. Majzik, and M. Massink, Automatic Verification of a Behavioural Subset of UML Statechart Diagrams Using the SPIN Model-checker, Formal Aspects of Computing, vol.11, issue.6, pp.637-664, 1999.
DOI : 10.1007/s001659970003

C. Lavarenne, O. Seghrouchni, Y. Sorel, and M. Sorine, The SynDEx software environment for real-time distributed systems, design and implementation, Proceedings of European Control Conference, ECC'91, p.64, 1991.

L. Beux, P. Marquet, O. Labbani, and J. Dekeyser, FPGA implementation of embedded cruise control and anti-collision radar, 9th Euromicro Conference on Digital System Design (DSD'2006), p.180, 2006.
URL : https://hal.archives-ouvertes.fr/inria-00079057

P. , L. Guernic, T. Gautier, M. L. Borgne, and C. L. Maire, Programming real-time applications with SIGNAL, Proceedings of the IEEE, vol.79, issue.9, pp.1321-1336, 1991.
URL : https://hal.archives-ouvertes.fr/inria-00075114

P. , L. Guernic, J. Talpin, and J. Lann, Polychrony for System Design, Journal for Circuits, Systems and Computers, vol.12, issue.87, pp.261-304, 2003.
URL : https://hal.archives-ouvertes.fr/hal-00730480

E. A. Lee and D. G. Messerschmitt, Synchronous data flow, Proceedings of the IEEE, pp.1235-1245, 1987.
DOI : 10.1109/PROC.1987.13876

R. Manduchi, G. M. Cortelazzo, and G. A. Mian, Multistage sampling structure conversion of video signals, IEEE Transactions on Circuits and Systems for Video Technology, vol.3, issue.5, pp.325-340, 1993.
DOI : 10.1109/76.246085

F. Maraninchi and Y. Rémond, Compositionality Criteria for Defining Mixed-Styles Synchronous Languages, International Symposium: Compositionality -The Significant Difference, p.78, 1997.
DOI : 10.1007/3-540-49213-5_16

F. Maraninchi and Y. Rémond, Mode-automata: About modes and states for reactive systems, European Symposium On Programming, p.97, 1998.
DOI : 10.1007/BFb0053571

F. Maraninchi and Y. Rémond, Argos: an automaton-based synchronous language, Computer Languages, vol.27, issue.1-3, pp.61-92, 2001.
DOI : 10.1016/S0096-0551(01)00016-9

URL : https://hal.archives-ouvertes.fr/hal-00273055

F. Maraninchi and Y. Rémond, Mode-Automata: a new domain-specific construct for the development of safe critical systems, Science of Computer Programming, vol.46, issue.3, pp.219-254, 2003.
DOI : 10.1016/S0167-6423(02)00093-X

H. Marchand, P. Bournai, M. L. Borgne, and P. L. Guernic, Synthesis of Discrete-Event Controllers based on the Signal Environment, Discrete Event Dynamic System: Theory and Applications, pp.325-346, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00546147

H. Marchand, E. Rutten, M. L. Borgne, and M. Samaan, Formal verification of programs specified with signal: application to a power transformer station controller, Science of Computer Programming, vol.41, issue.1, pp.85-104, 2001.
DOI : 10.1016/S0167-6423(00)00020-4

URL : https://hal.archives-ouvertes.fr/inria-00526287

C. Mauras, Alpha : un langage équationnel pour la conception et la programmation d'architectures parallèles synchrones, p.17, 1989.

M. Planet, Model-Driven Engineering, p.28

T. Mens and P. Van-gorp, A Taxonomy of Model Transformation, Proceedings of the International Workshop on Graph and Model Transformation, pp.125-142, 2005.
DOI : 10.1016/j.entcs.2005.10.021

M. Mernik, J. Heering, and A. M. Sloane, When and how to develop domain-specific languages, ACM Computing Surveys, vol.37, issue.4, pp.316-344, 2005.
DOI : 10.1145/1118890.1118892

J. Miller and J. Mukerji, Model Driven Architecture (MDA), p.33, 2001.

R. Milner, Calculi for synchrony and asynchrony, Theoretical Computer Science, vol.25, issue.3, pp.267-310, 1983.
DOI : 10.1016/0304-3975(83)90114-7

K. Praveen, E. A. Murthy, and . Lee, Multidimensional synchronous dataflow, IEEE Transactions on Signal Processing, vol.50, pp.3306-3309, 2002.

S. Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, 2003.

N. Pernet and Y. Sorel, A design method for implementing specifications including control in distributed embedded systems, 2005 IEEE Conference on Emerging Technologies and Factory Automation, p.64, 2005.
DOI : 10.1109/ETFA.2005.1612745

G. Perrin and A. Darte, The Data Parallel Programming Model: Foundations, HPF Realization, and Scientific Applications, Lecture Notes in Computer Science, vol.1132, 1996.
DOI : 10.1007/3-540-61736-1

E. Piel, Ordonnancement de systèmes parallèles temps-réel, Sciences et Technologies de Lille (USTL), 2007. 196 [111] M. Pouzet. Lucid synchrone: Reference manual

I. Quadri, S. Meftali, and J. Dekeyser, High Level Modeling of Partially Dynamically Reconfigurable FPGAs with MDE and MARTE, The Reconfigurable Communicationcentric Systems-on-Chip workshop, p.180, 2008.

F. Rocheteau, Extension du langage Lustre et application la conception de circuits: le langage Lustre-V4 et le système Pollux, pp.17-77, 1992.

E. Rutten and F. Martinez, SIGNAL GTi: implementing task preemption and time intervals in the synchronous data flow language SIGNAL, Proceedings Seventh Euromicro Workshop on Real-Time Systems, pp.176-183, 1995.
DOI : 10.1109/EMWRTS.1995.514309

D. Schmidt, Guest Editor's Introduction: Model-Driven Engineering, Computer, vol.39, issue.2, pp.25-31, 2006.
DOI : 10.1109/MC.2006.58

T. Schäfer, A. Knapp, and S. Merz, Model Checking UML State Machines and Collaborations, CAV 2001 Workshop on Software Model Checking, p.175, 2001.
DOI : 10.1016/S1571-0661(04)00262-2

B. V. Selic, On the semantic foundations of standard UML 2.0 Formal Methods for the Design of Real-Time Systems, International School on Formal Methods for the Design of Computer, Communication and Software Systems, Lecture Notes in Computer Science, vol.3185, p.33, 2004.

I. Smarandache, Transformations affines d'horloges: application au codesign de systèmes temps réel en utilisant les langages Signal et Alpha, p.59, 1998.

I. M. Smarandache, T. Gautier, and P. L. Guernic, Validation of mixed signal-alpha real-time systems through affine calculus on clock synchronisation constraints, World Congress on Formal Methods, pp.1364-1383, 1999.
DOI : 10.1007/3-540-48118-4_22

URL : https://hal.archives-ouvertes.fr/hal-00548887

J. Soula, Principe de Compilation d'un Langage de Traitement de Signal, French. 152 pages Julien Soula, p.73, 2001.

P. Stevens, A Landscape of Bidirectional Model Transformations, Summer school on Generative and Transformational Techniques in Software Engineering 2007 (GTTSE'07), p.31, 2007.
DOI : 10.1007/978-3-540-88643-3_10

S. Sundaram, More is more: Improvements in camera phone performance drive increased sales, Toshiba America Electronic Components, p.155, 2008.

J. Taillard, F. Guyomarc-'h, and J. Dekeyser, OpenMP code generation based on an Model-Driven Engineering approach, The 2008 High Performance Computing & Simulation Conference, 1924.

J. Talpin, C. Brunette, T. Gautier, and A. Gamatié, Polychronous mode automata, Proceedings of the 6th ACM & IEEE International conference on Embedded software , EMSOFT '06, pp.83-92, 2006.
DOI : 10.1145/1176887.1176900

URL : https://hal.archives-ouvertes.fr/hal-00541469

W. Team, Gaspard classic: Graphical array specification for parallel and distributed computing

W. Thies, M. Karczmarek, and S. P. Amarasinghe, StreamIt: A Language for Streaming Applications, CC '02: Proceedings of the 11th International Conference on Compiler Construction, pp.179-196, 2002.
DOI : 10.1007/3-540-45937-5_14

D. Wilde, The ALPHA Language, Technical Report, vol.827, 1994.
URL : https://hal.archives-ouvertes.fr/inria-00074378

W. Wolf, A decade of hardware/ software codesign, Computer, vol.36, issue.4, pp.38-43, 2003.
DOI : 10.1109/MC.2003.1193227

H. Yu, A. Gamatié, É. Rutten, P. Boulet, and J. Dekeyser, Vers des transformations d'applications à parallélisme de données en équations synchrones, 9ème édition de SYMPosium en Architectures nouvelles de machines(SympA'2006), p.24, 2006.

H. Yu, A. Gamatié, E. Rutten, and J. Dekeyser, Model Transformations from a Data Parallel Formalism Towards Synchronous Languages, p.169, 2007.
DOI : 10.1007/978-1-4020-8297-9_13

URL : https://hal.archives-ouvertes.fr/inria-00172302

H. Yu, A. Gamatié, E. Rutten, and J. Dekeyser, Embedded Systems Specification and Design Languages, Selected Contributions from FDL'07 Series, volume 10 of Lecture Notes Electrical Engineering, chapter 13: Model Transformations from a Data Parallel Formalism towards Synchronous Languages, pp.978-979, 2008.

H. Yu, A. Gamatié, É. Rutten, and J. Dekeyser, Safe design of high-performance embedded systems in an MDE framework, Innovations in Systems and Software Engineering (ISSE), p.173, 2008.
DOI : 10.1007/s11334-008-0059-y

H. Yu, A. Gamatié, É. Rutten, and J. Dekeyser, Safe design of high-performance embedded systems in an MDE framework, 1st IEEE International UML & Formal Methods workshop (UML&FM'08, p.169, 2008.
DOI : 10.1007/s11334-008-0059-y

A. Resolution and S. High, Medium init [RModeH=false; RModeM=true; RModeL=false;] Low [RModeH=false; RModeM=false; RModeL=true;] TRANS FROM High TO Medium WITH rien0 [(eRD and not eRU) or cR] FROM Medium TO Low WITH rien0 [(eRD and not eRU) or cR] FROM Low TO Medium WITH rien0 [eRU and not eRD and aR] FROM Medium TO High WITH rien0 [eRU and not eRD and aR