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Mise en œuvre de techniques de démonstration automatique pour la vérification formelle des NoCs

Abstract : The current technology allows the integration on a single die of complex systems-on-chip (SoC's) composed of manufactured blocks (IP's) that can be interconnected through specialized networks-on-chip (NoCs). IP's have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This thesis addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A meta-model for NoCs has been developed and implemented in ACL2. It satisfies generic correctness statements, which are logical consequences of a set of proof obligations for each one of the NoC constituents (topology, routing, switching technique,...). Thus the verification of a particular NoC instance is reduced to discharging this set of proof obligations. The purpose of this thesis is to extend this meta-model in several directions: more accurate timing modeling, flow control, priority mechanisms,... The methodology is demonstrated on realistic and state-of-the-art NoC designs: Spidergon (STMicroelectronics), Hermes (The Federal University of Rio Grande do Sul, Brazil, and LIRMM) , and Nostrum (Royal Institute Of Technology, Sweden) .
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Contributor : Lucie Torella <>
Submitted on : Wednesday, May 19, 2010 - 1:57:44 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
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  • HAL Id : tel-00484886, version 1




A. Helmy. Mise en œuvre de techniques de démonstration automatique pour la vérification formelle des NoCs. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨tel-00484886⟩



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