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Technique de BIST pour synthétiseurs de fréquence RF

Abstract : The expensive and time consuming RadioFrequency (RF) testers urge test optimization and alternative test methods for analog, mixed-signal RF circuits. Up to now, the test of RF circuits consisted in validating their functional specifications. Nevertheless, due to the increasing frequencies that come into play and the need to speed up test time, measurements of some functional specifications is no more feasible even on dedicated testers. The development of new methods is thus necessary to face these new requirements. This Ph.D. has the aim to be the first step towards building a set of universal BIST (Built-In Self Test) solutions for RF circuits to support design stage and optimize production test. BIST circuit validation is fault oriented. The validation strategy is based on the following steps: choice of test measures by simulation of the DUT (Device under Test); modeling of test measures and performances via Monte-Carlo simulations; generation of a statistically representative population through Copulas theory; generation of a list of faults that may occur in the DUT; fault injection simulations; analysis of test metrics such as fault coverage, the number of faulty circuits that pass the test (defect level), and the number of functional circuits that fail the test (yield loss). This work has been carried out on an industrial case study such as an RF PLL (Phase-Locked Loop) designed in STMicroelectronics.
keyword : BIST DfT PLL VCO
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Submitted on : Monday, May 10, 2010 - 2:06:17 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, September 16, 2010 - 1:23:08 PM

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  • HAL Id : tel-00482401, version 1

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A. Asquini. Technique de BIST pour synthétiseurs de fréquence RF. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2010. Français. ⟨tel-00482401⟩

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