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Logique programmable asynchrone pour systèmes embarqués sécurisés

Abstract : This thesis focuses on the design and the validation of an embedded FPGA dedicated to critical applications which require a high level of security and confidentiality. Nowadays FPGAs exhibit many weaknesses toward security: 1- They are not intended to efficiently support alternative styles of circuits such as asynchronous circuits. 2- The place and route flow is not completely manageable by the user in order to target our security goal. 3-They are not protected against side channel attacks such as DPA, EMA or DFA. In order to overcome these technological problems, the work presented in this thesis proposes an architecture that supports the programming of different styles of asynchronous circuits. In addition, it presents a secure programming system and a design that ensures a high-level of security against the attacks mentioned above. Finally, the circuit prototype has been evaluated in order to validate the relevance of the proposed solutions.
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Contributor : Lucie Torella <>
Submitted on : Friday, May 7, 2010 - 3:13:56 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Thursday, September 16, 2010 - 1:25:05 PM


  • HAL Id : tel-00481895, version 1




T. Beyrouthy. Logique programmable asynchrone pour systèmes embarqués sécurisés. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2009. Français. ⟨tel-00481895⟩



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