, Data consistency in hard real-time systems, 1993.
, A theory of timed automata, Theoretical Computer Science, vol.126, issue.2, pp.183-235, 1994.
DOI : 10.1016/0304-3975(94)90010-8
, Guaranteeing temporal validity with a realtime logic of knowledge, ICDCSW '03 : Proceedings of the 23rd Int'l Conf. on Distributed Computing Systems, pp.178-183, 2003.
, An old-fashioned recipe for real time, ACM Transactions on Programming Languages and Systems, vol.16, issue.5, pp.1543-1571, 1994.
DOI : 10.1145/186025.186058
, Time Modeling in MARTE, Forum on specification & Design Languages (FDL), pp.268-273
, Defining liveness, Information Processing Letters, vol.21, issue.4, pp.181-185, 1985.
DOI : 10.1016/0020-0190(85)90056-0
, Towards formalising AADL in Proof Assistants, Electronic Notes in Theoretical Computer Science, vol.141, issue.3, pp.153-169, 2005.
DOI : 10.1016/j.entcs.2005.05.008
URL : https://hal.archives-ouvertes.fr/hal-00784959
, The ESTEREL language, Research Report, 1991.
, Analyse temporelle des systèmes d'acquisition de données : une approche à base d'automates temporisés communicants et d'observateurs, Thèse de doctorat, pp.25-26, 2008.
, IF-2.0: A Validation Environment for Component-Based Real-Time Systems, Proceedings of Conference on Computer Aided Verification, CAV'02, pp.343-348, 2002.
DOI : 10.1007/3-540-45657-0_26
URL : https://hal.archives-ouvertes.fr/hal-00357518
, Formal evaluation of quality of service for data acquisition systems, Forum on specification and Design Languages, FDL'05, Proceedings, pp.579-589, 2005.
, Reachability problems and abstract state spaces for time petri nets with stopwatches. Discrete Event Dynamic Systems, pp.133-158, 2007.
DOI : 10.1007/s10626-006-0011-y
URL : https://hal.archives-ouvertes.fr/hal-00489016
, Synthesis of embedded software from synchronous dataflow specifications, The Journal of VLSI Signal Processing, vol.21, issue.2, pp.151-166, 1999.
DOI : 10.1023/A:1008052406396
, Temporal logics for real-time system specification, ACM Computing Surveys, vol.32, issue.1, pp.12-42, 2000.
DOI : 10.1145/349194.349197
, On the compared expressiveness of arc, place and transition time Petri nets, Fundamenta Informaticae, vol.88, issue.3, pp.225-249, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00489072
, Timed Automata: Semantics, Algorithms and Tools, pp.87-124, 2004.
DOI : 10.1007/978-3-540-27755-2_3
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.332.8701
, Specification and validation of multimedia protocols using RT-Lotos, Proceedings 5th Workshop on Future Trends in Distributed Computing Systems, pp.28-30, 1995.
, A MDA Approach for Systems Dedicated to Process Control, 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'05), pp.567-570, 2005.
DOI : 10.1109/RTCSA.2005.11
URL : https://hal.archives-ouvertes.fr/inria-00587341
, Formal Description Technique Lotos : Results of the Esprit Sedos Project, 1989.
, Quantitative temporal reasoning, CAV '90 : Proceedings of the 2nd International Workshop on Computer Aided Verification, pp.136-145, 1991.
DOI : 10.1007/bf00355298
, The architecture analysis and design language (AADL) : An introduction, 2006.
, Discrete-time dataflow models for visual simulation in Ptolemy II, 2001.
, Timed Automata with Asynchronous Processes: Schedulability and Decidability, TACAS '02 : Proceedings of the 8th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, pp.67-82, 2002.
DOI : 10.1007/3-540-46002-0_6
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.108.8710
, The synchronous dataflow programming language LUSTRE, Proceedings of the IEEE, pp.1305-1320, 1991.
, Communicating sequential processes, Communications of the ACM, vol.21, issue.8, pp.666-677, 1978.
, Spin model checker, the : primer and reference manual, 2003.
, The temporal logic of actions, ACM Transactions on Programming Languages and Systems, vol.16, issue.3, pp.872-923, 1994.
, Scheduling algorithms for multiprogramming in a hard-real-time environment, 1973.
, A Data Oriented Approach for Real-Time Systems, International Conference on Real-Time and Network Systems (RTNS), 2009.
URL : https://hal.archives-ouvertes.fr/inria-00442001
, Uppaal in a nutshell, International Journal on Software Tools for Technology Transfer, vol.1, issue.1-2, pp.134-152, 1997.
DOI : 10.1007/s100090050010
, Comparing models of computation, Proceedings of International Conference on Computer Aided Design, pp.234-241, 1996.
DOI : 10.1109/ICCAD.1996.569613
, Formal modelling framework of data acquisition modules using a synchronous approach for timing analysis, Proceedings of the 30th IFAC Workshop on Real-Time Programming and 4th International Workshop on Real-Time Software, pp.123-130, 2009.
, A study of the recoverability of computing systems, 1974.
, A Calculus of Communicating Systems, 1982.
, Analysis of asynchronous concurrent systems by timed petri nets, 1974.
, A timed model for communicating sequential processes, Theoretical Computer Science, vol.58, issue.1-3, pp.249-261, 1988.
DOI : 10.1016/0304-3975(88)90030-8
, Priority inheritance protocols: an approach to real-time synchronization, IEEE Transactions on Computers, vol.39, issue.9, pp.1175-1185, 1990.
DOI : 10.1109/12.57058
, Misconceptions about real-time computing : a serious problem for next-generation systems, Computer, vol.21, pp.10-19, 1988.
, Holistic schedulability analysis for distributed hard real-time systems. Microprocessing and Microprogramming -Euromicro Journal (Special Issue on Parallel Embedded Real-Time Systems), pp.117-134, 1994.
DOI : 10.1016/0165-6074(94)90080-9
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.2371
, Automata on infinite objects, pp.133-191, 1990.
, Scheduling transactions with temporal constraints : exploiting data semantics, RTSS '96 : Proceedings of the 17th IEEE Real-Time Systems Symposium, pp.240-253, 1996.
, CCS + time = an interleaving model for real time systems, Proceedings of the 18th international colloquium on Automata, languages and programming, pp.217-228, 1991.
, Cette trace correspond à une exécution infinie prouvant la satisfiabilité de la spécification
, 2>>>> STATE 3: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 5: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 7: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 9: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> 194 STATE 13: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 15: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 19: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, 2>>>> STATE 21: <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1
, <Action line 116, col 9 to line 121, col 20 of module exemple3>, p.1