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Contribution à l'étude de techniques de siliciuration avancées pour les technologies CMOS décananométriques

Abstract : In the context of the CMOS technology scaling, the junction module appears as being critical for the device performance improvement. Indeed, the Schottky barrier height between the silicide and the silicon is a main limitation for the on-state current increase. This thesis addresses the problem of barrier height control following two main paths. On the one hand, we study the impact of a modification of the metal forming the silicide. On another hand, we evaluate the potential of barrier height modulation using dopant segregation techniques. The difficulties related to the integration of n-type silicides (e.g. ErSi) are highlighted as well. Also, the strong potential of the PtSi is demonstrated. This silicide intrinsically shows a better thermal stability as compared to the reference silicide (NiSi), and has a low barrier height to holes. Moreover, we implement a method using dopant segregation techniques that allow us to reach low barrier heights to electrons. PtSi thus appears as a promising candidate for future CMOS technologies. However, we underline the strong issues related to the self-aligned integration of PtSi using the aqua regia standard process. We have developed during this thesis a new selective etching method based on the transformation of the unreacted metal into a germanide, easily etchable in conventional chemistries, that allows a safe integration. As a conclusion, we integrate PtSi in an industrial process flow, and we demonstrate that electrical performance are in-line with state-of-the-art CMOS technologies.
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https://tel.archives-ouvertes.fr/tel-00460287
Contributor : Nicolas Breil <>
Submitted on : Friday, February 26, 2010 - 4:14:35 PM
Last modification on : Tuesday, December 8, 2020 - 3:32:33 AM
Long-term archiving on: : Friday, June 18, 2010 - 8:27:28 PM

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  • HAL Id : tel-00460287, version 1

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Nicolas Breil. Contribution à l'étude de techniques de siliciuration avancées pour les technologies CMOS décananométriques. Micro et nanotechnologies/Microélectronique. Université des Sciences et Technologie de Lille - Lille I, 2009. Français. ⟨tel-00460287⟩

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