Abstract : Hardware verification has become challenging due to ever-growing complexity of today's designs. We aim at assisting verification of hardware intellectual property (IP) modules at register transfer level (RTL) by means of data abstraction and static formal analysis techniques. We believe that before applying data abstraction, it is necessary to clearly define and separate the Control and Data processing of modules. The consideration of control and data in hardware has previously been a subjective judgment of the designer, based on the syntax. We intuitively define the "Control" as an entity responsible for the timings of the data operations in IP modules. The proposed definition was envisaged for separating Control and Data, independent of the subjective choice or the specific syntax. We have worked around a few semantic issues of the definition and demonstrated by reasoning, that an ideal separation of control and data is not achievable according to the proposed definition due to the syntax dependent boolean computations. We therefore, separate the Control and Data based on designer's knowledge. A control-data slicing algorithm is proposed to split the module into a control slice and a data slice which meets our desired goal of data abstraction. An abstraction is achieved in case of slicing with data-independent control. The bit accurate RTL data slice is replaced by a functional data computation model for fast simulations. The control slice being critical entity with timing information, remains intact during this process. This provides us a way of abstracting the data processing and considering only the timing information for formal verification. We have proposed the notion of significance to represent the intentional data in IP modules. Significance is used to represent boolean data dependencies in modules for formal verification of the data flows. Approximations to data dependencies in IP modules have been realized with demonstration of their correctness. The verification technique based on significance is realized which enables to formally verify properties related to the datapaths.