du temps de propagation sur une interconnexion. T p1 représente la différence de temps entre le passage à 50% de la transition par rapport à sa valeur finale de la porte en entrée et le passage à 50% de la transition par rapport à sa valeur finale de la porte en sortie. T p2 représente la différence entre le temps de passage de 10% à 90% par rapport à sa valeur finale de la transition de la porte en sortie, p.29 ,
Irredundant address bus encoding for low power, the Proceedings of the 2001 international symposium on Low power electronics and design (ISLPED), pp.182-187, 2001. ,
Impact of copper dummies on interconnect propagation performance in advanced integrated circuits, Microelectronic Engineering, vol.76, issue.1-4, pp.1-4119, 2004. ,
DOI : 10.1016/j.mee.2004.07.004
Optimal interconnection circuits for VLSI, IEEE Transactions on Electron Devices, vol.32, issue.5, pp.903-909, 1985. ,
DOI : 10.1109/T-ED.1985.22046
Asymptotic zerotransition activity encoding for address busses in low-power microprocessor-based systems, the Proceedings of the 7th Great Lakes Symposium on VLSI (GLS), p.77, 1997. ,
Address bus encoding techniques for system-level power optimization, the Proceedings of the conference on Design, automation and test in Europe (DATE), pp.861-867, 1998. ,
On-chip copper-based vs. optical interconnects : Delay uncertainty, latency, power, and bandwidth density comparative predictions, International Interconnect Technology Conference, pp.39-41, 2006. ,
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.14, issue.2, pp.161-172, 2006. ,
DOI : 10.1109/TVLSI.2005.863750
Segmented bus design for low-power systems, IEEE Trans. on Very Large Scale Integration Systems, vol.7, issue.1, pp.25-29, 1999. ,
Estimation et optimisation de la consommation des interconnexions dans les soc, the 1st GDR SOC SIP symposium, 2007. ,
URL : https://hal.archives-ouvertes.fr/hal-00294145
Modélisation, estimation et optimisation de la consommation des interconnexions dans les soc, the 2nd GDR SOC SIP symposium, 2008. ,
New directions in interconnect performance optimization, 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp.1-6, 2008. ,
Modélisation et estimation de la consommation des interconnexions dans les soc, the Proceedings of the Faible Tension Faible Consommation conference (FTFC), pp.121-125, 2007. ,
Novel cross-transition elimination technique improving delay and power consumption for on-chip buses, the Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2008. ,
Procédé et dispositif de codage, système électronique et support d'enregistrement associés. Patent Pending, 2008. ,
Interconnexions et consommation : où en sommes nous ?, the Proceedings of the 4th MajecSTIC, 2006. ,
High-level interconnect delay and power estimation, Journal of Low Power Electronics, vol.4, issue.1, pp.21-33, 2008. ,
Interconnect explorer : a highlevel estimation tool for on-chip interconnects, 2008. ,
Digital Systems Engineering, 1998. ,
DOI : 10.1017/CBO9781139166980
Demystifying 3D ICs: The Pros and Cons of Going Vertical, IEEE Design and Test of Computers, vol.22, issue.6, pp.22498-510, 2005. ,
DOI : 10.1109/MDT.2005.136
The transient response of damped linear networks with particular regard to wideband amplifiers, Journal of Applied Physics, vol.19, pp.55-63, 1948. ,
Power optimization of system-level address buses based on software profiling, Proceedings of the eighth international workshop on Hardware/software codesign , CODES '00, pp.29-33, 2000. ,
DOI : 10.1145/334012.334018
Electrical properties of ideal carbon nanotubes, 5th IEEE Conference on Nanotechnology, pp.677-680, 2005. ,
Interface exploration for reduced power in core-based systems, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210), pp.117-122, 1998. ,
DOI : 10.1109/ISSS.1998.730611
The future of wires, Proceedings of the IEEE, vol.89, issue.4, pp.490-504, 2001. ,
DOI : 10.1109/5.920580
A bus delay reduction technique considering crosstalk, the Proceedings of the conference on Design, automation and test in Europe (DATE), pp.441-445, 2000. ,
Figures of merit to characterize the importance of on-chip inductance, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, issue.4, pp.442-449, 1999. ,
DOI : 10.1109/92.805751
Crosstalk Noise Immune VLSI Design Regular Layout Fabrics, 1978. ,
Low power chip interface based on bus data encoding with adaptive code-book method, Proceedings Ninth Great Lakes Symposium on VLSI, pp.368-371, 1999. ,
DOI : 10.1109/GLSV.1999.757458
Dummy filling methods for reducing interconnect capacitance and number of fills, the Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED), pp.586-591, 2005. ,
Why transition coding for power minimization of on-chip buses does not work, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.10512-10517, 2004. ,
DOI : 10.1109/DATE.2004.1268897
On-chip optical interconnects, Intel Technology Journal, vol.8, issue.2, pp.129-141, 2005. ,
Optimal wire sizing and buffer insertion for low power and a generalized delay model, the Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design (ICCAD), pp.138-143, 1995. ,
A dictionary-based en/decoding scheme for low-power data buses, IEEE Trans. on Very Large Scale Integration Systems, vol.11, issue.5, pp.943-951, 2003. ,
Layout impact of resolution enhancement techniques : impediment or opportunity ?, the Proceedings of the 2003 international symposium on Physical design (ISPD), pp.110-117, 2003. ,
An optimized output stage for mos integrated circuits, IEEE Journal of Solid-State Circuits, vol.10, pp.106-109, 1975. ,
Global Interconnect Width and Spacing Optimization for Latency, Bandwidth and Power Dissipation, IEEE Transactions on Electron Devices, vol.52, issue.10, pp.2272-2279, 2005. ,
DOI : 10.1109/TED.2005.856795
Architectural power analysis: The dual bit type method, Conway. Introduction to VLSI Systems, pp.173-187, 1980. ,
DOI : 10.1109/92.386219
Interconnect-power dissipation in a microprocessor, Proceedings of the 2004 international workshop on System level interconnect prediction , SLIP '04, pp.7-13, 2004. ,
DOI : 10.1145/966747.966750
Wire placement for crosstalk energy minimization in address buses, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, pp.158-162, 2002. ,
DOI : 10.1109/DATE.2002.998264
Cramming more components onto integrated circuits, Electronics, vol.38, issue.8, pp.114-117, 1965. ,
Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000. ,
DOI : 10.1109/ISCAS.2000.856173
Optimal wire sizing and buffer insertion for low power and a generalized delay model, the Proceedings of the IEEE international conference on ASIC/SOC, 2001. ,
Driving large capacitance in mos lsi systems, IEEE Trans. of Solid-State Circuits, vol.19, issue.1, pp.159-161, 1984. ,
Monolayer metallic nanotube interconnects: promising candidates for short local interconnects, IEEE Electron Device Letters, vol.26, issue.8, pp.544-546, 2005. ,
DOI : 10.1109/LED.2005.852744
Area Efficient Temporal Coding Schemes for Reducing Crosstalk Effects, 7th International Symposium on Quality Electronic Design (ISQED'06), pp.334-339, 2006. ,
DOI : 10.1109/ISQED.2006.28
Predictive Technology Model, 2007. ,
Digital Integrated Circuits : A design perspective, 2003. ,
Closed-form expressions for interconnection delay, coupling, and crosstalk in vlsi's, IEEE Trans on Electron. Devices, pp.118-124, 1993. ,
Bus-invert coding for low-power I/O, IEEE Trans. on Very Large Scale Integration Systems, pp.49-58, 1995. ,
DOI : 10.1109/92.365453
Partial bus-invert coding for power optimization of system level bus, Proceedings of the 1998 international symposium on Low power electronics and design , ISLPED '98, pp.127-129, 1998. ,
DOI : 10.1145/280756.280829
Cache design trade-offs for power and performance optimization, Proceedings of the 1995 international symposium on Low power design , ISLPED '95, pp.63-68, 1995. ,
DOI : 10.1145/224081.224093
Dynamic voltage scaling with links for power optimization of interconnection networks, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings., pp.91-102, 2003. ,
DOI : 10.1109/HPCA.2003.1183527
Saving power in the control path of embedded processors. Design and Test of Computers, pp.24-31, 1994. ,
Modeling and minimization of interconnect energy dissipation in nanometer technologies, Proceedings of the 38th conference on Design automation , DAC '01, pp.754-757, 2001. ,
DOI : 10.1145/378239.379060
The future of interconnction technology, IBM J. Research and Development, vol.44, issue.3, 2000. ,
High-Level Interconnect Delay and Power Estimation, Journal of Low Power Electronics (JOLPE), vol.4, issue.1, pp.21-33, 2008. ,
Novel Cross-Transition Elimination Technique Improving Delay and Power Consumption for On-Chip Buses, Conférences internationales avec comité de lecture ,
New directions in interconnect performance optimization, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.1-6, 2008. ,
DOI : 10.1109/DTIS.2008.4540228
URL : https://hal.archives-ouvertes.fr/hal-00294132
Modélisation et estimation de la consommation des interconnexions dans les SOC, Conférences nationales avec comité de lecture the Proceedings of the Faible Tension Faible Consommation conference (FTFC)CSJ06] A. Courtay and O. Sentieys and N. Julien. Interconnexions et consommation : où en sommes nous ? In the 4th MajecSTIC conference (MajecSTIC), pp.121-125, 2006. ,