Skip to Main content Skip to Navigation

Consommation d'énergie dans les interconnexions sur puce : Estimation de haut niveau et optimisations architecturales

Abstract : Nowadays, nomad applications are more and more complex and require many computationnal ressources, which involve a large amount of data to be stored or translated from a unit to another. Moreover, with technological parameters evolution, controlling propagation time and power consumption of SoC's interconnects becomes a major issue. ITRS's predictions show wire and transistor dimensions shrinking, which imply a circuit behaviour modification ; especially with propagation time. Today the wire propagation time becomes higher than the gate one. This increase is among other things, due to the increase of interconnect's resistance and capacitance. The capacitance increase also involves a power consumption increase due to interconnects which can represents up to 50% of the total chip power consumption and area. So it is now necessary to take interconnect's power consumption into acount during the chip power consumption evaluation. To do this, accurate physical interconnects models and power consumption estimation tools have to be proposed to enable designers having reliable results on the chip design. In the first chapter of this thesis, physical bus modeling for power consumption modeling is discussed. Distributed resistance and capacitance wire has first be caracterized, then for buses, buffers and crosstalk capacitances have been considered. In the second chapter, the interconnect power consumption estimation methodology is disscussed. As the bus has been physically modeled, important parameters that impact power consumption (technology, metal layer, bus length . . .) have been extracted. Finally, SPICE simulations of the circuits have been done ; experimental results provided by the simulations have allowed us to realise some models which have been included in our estimation tool. Our tool (Interconnect Explorer) allow users, after configuration (which means choosing a technology, a metal layer, a bus length and so on) to obtain rapidely a power consumption estimation of the considered bus. Validation experimentations show that the maximum error of the estimation tool is 3% (compared to SPICE simulations) with a few seconds execution time (a SPICE simulation in the same experimental conditions can last few hours). In the third chapter, a state of the art of the major power and timing optimization techniques is proposed. Interconnect Explorer allows us to validate the techniques efficiency on the power consumption impacting parameters (activity, propagation time, parasitic capacitances . . .). Then, the analysis of the results provided by Interconnect Explorer allows us to demonstrate that optimization techniques do not face all good criterias. At the chapter end, some new ways for interconnect power consumption optimization are proposed. The fourth chapter of this thesis presents our power consumption optimization techniques according to the issues disscussed in the previous chapter. The particularity of these techniques (one of them called the Spatial Switching is patented) is that they have a low material overhead. Many methodologies proposed in the state of the art have a quite high material overhead, particularly due to their codecs. These codecs lead to a power consumption overhead often higher than the power consumption reduction they can lead on the bus for usual SoC interconnect length. Our Spatial Switching experimental results show energetic power consumption gains that can rise up to 12% for a 5mm bus in the 65nm technology. These results include, of course, the extra power consumption due to the codecs. Gains rise more with technological steps and bus length increase. We will also propose a possible extension of our work (tool and models) by the abstracton level elevation. In our work, point to point interconnects have been considered ; but, present systems can use more complex communication schemes. First, our approach can be used to model MESH or NoC interconnects that are often use in MPSoC systems. Experimental results will be extracted from the simulation of MPSoC architectures using the SocLib platform. Then, these results can be extended to be used in a MDE (Model Driven Engineering) approach. In this context, our work will be included in the ITEA SPICES project using an AADL profile (Application & Architecture Design Language). The goal is, here, to use our results in the OSATE (Open Source AADL Tool Environment) framework to allow the power consumption estimations during the first design phases of the system. As interconnect power consumption has become a major issue in SoC design, this thesis will be concluded by a presentation of the emerging interconnect design solutions (optical interconnects, 3D SoC, carbon nanotubes. . .) and how our work can be applied on these technologies.
Complete list of metadata

Cited literature [60 references]  Display  Hide  Download
Contributor : Antoine Courtay Connect in order to contact the contributor
Submitted on : Monday, January 11, 2010 - 1:17:46 PM
Last modification on : Monday, October 11, 2021 - 2:22:30 PM
Long-term archiving on: : Thursday, June 17, 2010 - 10:37:04 PM


  • HAL Id : tel-00445791, version 1


Antoine Courtay. Consommation d'énergie dans les interconnexions sur puce : Estimation de haut niveau et optimisations architecturales. Sciences de l'ingénieur [physics]. Université de Bretagne Sud, 2008. Français. ⟨tel-00445791⟩



Record views


Files downloads