Skip to Main content Skip to Navigation

Étude et optimisation de l'interaction processeurs-architectures reconfigurables dynamiquement

Ben Abdallah Faten 1
1 CAIRN - Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources
IRISA-D3 - ARCHITECTURE, Inria Rennes – Bretagne Atlantique
Abstract : Telecommunication applications, especially in embedded systems, have become more complicated and so require more resources to accelerate calculation and reduce power consumption. To satisfy these requirements, system designers are looking to hybrid architectures which associate different systems with different paradigms. These new architectures deserve more attention because they permit interesting calculation cost/performance compromise and attractive power consumption properties. Furthermore, the Dynamic Reconfigurable Architectures, giving high performances and more flexibility during the last decade, have been associated to one or several processors to create the new hybrid-architecture generations. This thesis treats this area and presents a new and precise modelisation for these architectures. The document gives also methodologies permitting their high performance exploit. First, this document details a modelisation of information exchange process between a processor and a reconfigurable unit. This modelisation has permitted a precise identification of different performance criteria. Using these latter, we present an algorithm/architecture adequacy. It allows the determination of the CPU/ARD coupling kind depending on the application parameters. In the second part, we introduce these performance criteria in the hybrid-architecture software development flow to permit an automatic timing partitioning. This partitioning is based on the ARD surface determination (in terms of functional-unit number) required to obtain optimum level performances. It is feasible by the loop unrolling factor calculation which guarantees a high level performance for the hybrid architecture. The last part of this document concerns the validation of these proposed methodologies. For that, we present the exploration and the implementation process of a DVB-T/H demodulator and a WCDMA dynamic receiver on an dynamically reconfigurable hybrid architecture.
Complete list of metadatas
Contributor : Olivier Sentieys <>
Submitted on : Friday, December 4, 2009 - 10:53:28 AM
Last modification on : Wednesday, December 18, 2019 - 4:57:41 PM
Document(s) archivé(s) le : Thursday, June 17, 2010 - 11:08:40 PM


  • HAL Id : tel-00438608, version 1


Ben Abdallah Faten. Étude et optimisation de l'interaction processeurs-architectures reconfigurables dynamiquement. Micro et nanotechnologies/Microélectronique. Université Rennes 1, 2009. Français. ⟨tel-00438608⟩



Record views


Files downloads