était d'implanter SHA-256, 384 et 512 dans un unique opérateur avec pour cible le Virtex XCV200. Lors d'un calcul de la fonction SHA-256, la moitié du chemin de donnée (donc du matériel) reste inutilisée ,
32 (pour = 64 bits) cycles sont exigés pour acquérir et remplir chaque bloc du message avant que ce bloc ne soit haché. À ceci s'ajoute un cycle pour le contrôle. Ces cycles supplémentaires sont évités dans le système proposé ici, qui grâce un traitement « au vol » des données demande 25% de cycles en moins que [56] pour traiter chaque bloc. De plus ,
Évaluation de polynômes et de fractions rationnelles sur FPGA avec des opérateurs à base d'additions et décalages en grande base, Remerciements Ces travaux ont été en partie financés grâce à l'iCORE le NSERC (Natural Sciences and Engineering Research Council of Canada), pp.85-96, 2005. ,
Étude statistique de l'activité de la fonction de sélection dans l'algorithe de E-méthode. Dans 5 e journées d'études Faible Tension Faible Consommation (FTFC), pp.61-65, 2005. ,
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), pp.334-339, 2005. ,
DOI : 10.1109/ASAP.2005.59
URL : https://hal.archives-ouvertes.fr/inria-00070504
New identities and transformations for hardware power operators, Advanced Signal Processing Algorithms, Architectures, and Implementations XVI, 2006. ,
DOI : 10.1117/12.676244
URL : https://hal.archives-ouvertes.fr/lirmm-00125518
Divgen : a divider unit generator, Advanced Signal Processing Algorithms, Architectures and Implementations XV. SPIE, 2005. ,
Multi-mode operator for SHA-2 hash functions, International Conference on Engineering of Reconfigurable Systems & Algorithms, pp.207-210, 2006. ,
DOI : 10.1016/j.sysarc.2006.09.006
URL : https://hal.archives-ouvertes.fr/lirmm-00125521
Multi-mode operator for SHA-2 hash functions, Journal of Systems Architecture, vol.53, issue.2-3, pp.127-138, 2007. ,
DOI : 10.1016/j.sysarc.2006.09.006
URL : https://hal.archives-ouvertes.fr/lirmm-00125521
Optimisation d'op??rateurs arithm??tiques mat??riels ?? base d'approximations polynomiales, 11 e SYMPosium en Architectures nouvelles de machines (SYMPA), pp.130-141, 2006. ,
DOI : 10.3166/tsi.27.699-718
Carry Prediction and Selection for Truncated Multiplication, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006. ,
DOI : 10.1109/SIPS.2006.352605
URL : https://hal.archives-ouvertes.fr/lirmm-00153366
Digital Arithmetic, 2003. ,
URL : https://hal.archives-ouvertes.fr/ensl-00542215
Elementary Functions : Algorithms and Implementation. Birkhäuser, 2 e édition, 2006. ,
URL : https://hal.archives-ouvertes.fr/ensl-00000008
Computer Arithmetic : Algorithms and Hardware Designs, 2000. ,
Computing machine-efficient polynomial approximations, ACM Transactions on Mathematical Software, vol.32, issue.2, pp.236-256, 2006. ,
DOI : 10.1145/1141885.1141890
URL : https://hal.archives-ouvertes.fr/ensl-00086826
Polynomial evaluation in VLSI using distributed arithmetic, IEEE Transactions on Circuits and Systems, vol.37, issue.10, pp.1299-1304, 1990. ,
DOI : 10.1109/31.103226
Multipartite table methods, IEEE Transactions on Computers, vol.54, issue.3, pp.319-330, 2005. ,
URL : https://hal.archives-ouvertes.fr/ensl-00542210
Hardwired polynomial evaluation, Journal of Parallel and Distributed Computing, vol.5, issue.3, pp.291-309, 1988. ,
DOI : 10.1016/0743-7315(88)90022-6
Reciprocation, square root, inverse square root, and some elementary functions using small multipliers, IEEE Transactions on Computers, vol.49, issue.7, pp.628-637, 2000. ,
DOI : 10.1109/12.863031
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.30.7789
Sur un procédé convergent d'approximations successives pour déterminer les polynômes d'approximation. Comptes Rendus de l'Académie des Sciences de Paris, pp.2063-2065, 1934. ,
Approximating elementary functions with symmetric bipartite tables, IEEE Transactions on Computers, vol.48, issue.8, pp.842-847, 1999. ,
DOI : 10.1109/12.795125
Powering by a table look-up and a multiplication with operand modification, IEEE Transactions on Computers, vol.47, issue.11, pp.1216-1222, 1998. ,
DOI : 10.1109/12.736432
Handbook of Writing for the Mathematical Sciences, Society for Industrial and Applied Mathematics, 1998. ,
The Art of Computer Programming, Volume III : Sorting and Searching, 1973. ,
IA-64 and Elementary Functions : Speed and Precision. Hewlett-Packard Professional Books, 2000. ,
Numerical Recipes in C : The Art of Scientific Computing, 1992. ,
Second Order Function Approximation Using a Single Multiplication on FPGAs, 14th International Conference on Field-Programmable Logic and Applications (FPL), numéro 3203 de LNCS, pp.221-230, 2004. ,
DOI : 10.1007/978-3-540-30117-2_24
Table-based polynomials for fast hardware function evaluation, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05), pp.328-333, 2005. ,
DOI : 10.1109/ASAP.2005.61
Function evaluation by table look-up and addition, Proceedings of the 12th Symposium on Computer Arithmetic, pp.10-16, 1995. ,
DOI : 10.1109/ARITH.1995.465382
Approximation of Elementary Functions Using a Weighted Sum of Bit-Products, 2006 IEEE International Symposium on Circuits and Systems, pp.795-798, 2006. ,
DOI : 10.1109/ISCAS.2006.1692705
SWARTZLANDER : Data-dependent truncation scheme for parallel multipliers, 31th Asilomar Conference on Signals, Systems & Computers, pp.1178-1182, 1997. ,
Parallel square and cube computations, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154), pp.1325-1329, 2000. ,
DOI : 10.1109/ACSSC.2000.911207
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.33.6907
Faithful powering computation using table look-up and a fused accumulation tree, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.40-47, 2001. ,
DOI : 10.1109/ARITH.2001.930102
Design of a 32-bit squarer - exploiting addition redundancy, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., pp.325-328, 2003. ,
DOI : 10.1109/ISCAS.2003.1206269
Bit-serial multipliers and squarers, IEEE Transactions on Computers, vol.43, issue.12, pp.1445-1450, 1994. ,
DOI : 10.1109/12.338107
A subword-parallel multiplication and sum-of-squares unit, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.19-20, 2004. ,
Improved small multiplier based multiplication, squaring and division, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003., pp.91-97, 2003. ,
DOI : 10.1109/FPGA.2003.1227245
Efficient Function Approximation Using Truncated Multipliers and Squarers, 17th IEEE Symposium on Computer Arithmetic (ARITH'05), pp.232-239, 2005. ,
DOI : 10.1109/ARITH.2005.18
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.517.5476
SHIEH : Design of a high-speed square generator, IEEE Transactions on Computers, vol.47, issue.9, pp.1021-1026, 1998. ,
BALZOLA : Combined unsigned and two's complement squarers, 33th Asilomar Conference on Signals, Systems & Computers, pp.1215-1219, 1999. ,
DOI : 10.1109/acssc.1999.831900
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.36.8201
The Mathematics of the Pentium Division Bug, SIAM Review, vol.39, issue.1, pp.54-67, 1997. ,
DOI : 10.1137/S0036144595293959
On-the-Fly Conversion of Redundant into Conventional Representations, IEEE Transactions on Computers, vol.36, issue.7, pp.895-897, 1987. ,
DOI : 10.1109/TC.1987.1676986
On-the-fly rounding (computing arithmetic), IEEE Transactions on Computers, vol.41, issue.12, pp.1497-1503, 1992. ,
DOI : 10.1109/12.214659
Digit selection for SRT division and square root, IEEE Transactions on Computers, vol.54, issue.3, pp.294-303, 2005. ,
DOI : 10.1109/TC.2005.47
Radix-4 reciprocal square-root and its combination with division and square root, IEEE Transactions on Computers, vol.52, issue.9, pp.1100-1114, 2003. ,
DOI : 10.1109/TC.2003.1228508
Design issues in division and other floating-point operations, IEEE Transactions on Computers, vol.46, issue.2, pp.154-161, 1997. ,
DOI : 10.1109/12.565590
Division algorithms and implementations, IEEE Transactions on Computers, vol.46, issue.8, pp.833-854, 1997. ,
DOI : 10.1109/12.609274
Minimizing the complexity of SRT tables, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.6, issue.1, pp.141-149, 1998. ,
DOI : 10.1109/92.661256
A new class of division methods, IRE Transactions Electronic Computers, issue.7, pp.218-222, 1958. ,
A VLSI algorithm for computing the euclidean norm of a 3d vector, IEEE Transactions on Computers, vol.49, issue.10, pp.1074-1082, 2000. ,
Division and Square Root : Digit-Recurrence Algorithms and Implementations, 1994. ,
Algorithms for high speed shared radix 4 division and radix 4 square root, 8th IEEE Symposium on Computer Arithmetic (ARITH8), pp.73-79, 1987. ,
A hardware algorithm for computing reciprocal square root, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001, pp.94-100, 2001. ,
DOI : 10.1109/ARITH.2001.930108
Efficient permutation instructions for fast software cryptography, IEEE Micro, vol.21, issue.6, pp.56-69, 2001. ,
DOI : 10.1109/40.977759
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.454.6172
Implementation of the SHA-2 Hash Family Standard Using FPGAs, The Journal of Supercomputing, vol.31, issue.3, pp.227-248, 2005. ,
DOI : 10.1007/s11227-005-0086-5
Efficient single-chip implementation of SHA-384 and SHA-512, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings., pp.311-314, 2002. ,
DOI : 10.1109/FPT.2002.1188699
Finding Collisions in the Full SHA-1, Lecture Notes in Computer Science, vol.3621, pp.17-36, 2005. ,
DOI : 10.1007/11535218_2
The Design of Rijndael : AES -The Advanced Encryption Standard, 2002. ,
DOI : 10.1007/978-3-662-04722-4
VANSTONE : Handbook of Applied Cryptography, 1997. ,
FIPS PUB 180-1 : Secure Hash Standard, NIST, 1995. ,
FIPS PUB 180-2 : Secure Hash Standard, NIST, 2004. ,
Tiger: A fast new hash function, IWFSE : International Workshop on Fast Software Encryption, 1996. ,
DOI : 10.1007/3-540-60865-6_46
RIPEMD-160: A strengthened version of RIPEMD, IWFSE : International Workshop on Fast Software Encryption, 1996. ,
DOI : 10.1007/3-540-60865-6_44
The WHIRLPOOL hash function. document World- Wide Web, 2001. ,
Collisions for hash functions MD4, MD5, HAVAL- 128 and RIPEMD, Cryptology ePrint Archive Report, 2004. ,