A. Kouadri, B. Senouci, and F. Pétrot, Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform, Liste des Publications Publication internationales Digital System Design Architectures, Methods and Tools, pp.3-9, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00349055

B. Senouci, A. Kouadri, F. Rousseau, and F. Petrot, Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers RSP '08. The 19th IEEE, Rapid System PrototypingIFIP International Symposium on, pp.41-47, 2008.
DOI : 10.1109/rsp.2008.27

A. Kouadri, B. Senouci, and F. Petrot, Networks-In-Package: Performances management and design methodology, VLSI-DAT 2008. IEEE International Symposium on, pp.140-143, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00349052

A. Kouadri, B. Senouci, and F. Petrot, Scalable Multi-FPGA Platform for Networks-On- Chip Emulation, Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on, pp.54-60, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00264982

F. Colloques-nationaux-pétrot and A. Kouadri, From Networks-On-Chip Emulation to Networks-In-Package Synthesis, French Winter School on Heterogeneous Embedded Systems Design, pp.7-9, 2008.

A. Kouadri and F. Pétrot, Flexible Architectures for HW/SW Interfaces " French Winter School on Heterogeneous Embedded Systems Design, Villard-de, 2007.

D. Micheli, G. Benini, and L. , Networks on chip: a new paradigm for systems on chip design, Europe Conference and Exhibition, 2002. Proceedings, pp.418-419, 2002.

A. Baghdadi, N. Zergainoh, W. Cesario, T. Roudier, and A. A. Jerraya, Design space exploration for hardware/software codesign of multiprocessor systems, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2000.
DOI : 10.1109/IWRSP.2000.854975

URL : https://hal.archives-ouvertes.fr/hal-00008096

K. Lahiri, A. Raghunathan, and S. Dey, Design Space Exploration for Optimizing On-Chip Communication Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23, issue.6, pp.952-961, 2004.
DOI : 10.1109/TCAD.2004.828127

K. Goossens, Formal methods for networks on chips Application of Concurrency to System Design, Fifth International Conference on, pp.188-189, 2005.

R. Marculescu, H. Jingcao, and U. Y. Ogras, Key research problems in NoC design: a holistic perspective, Hardware/Software Codesign and System Synthesis Third IEEE/ACM/IFIP International Conference on, pp.69-74, 2005.

J. Marti, Large Tandem Queueing Networks with Blocking Queueing Systems: Theory and Applications, v.41 n.1-2, Interopérabilité en Emulation et Prototypage Matériel, pp.45-72, 2002.

A. Kouadri, B. Senouci, and F. Pétrot, Networks-In-Package: Performances management and design methodology, IEEE International Symposium on, pp.140-143, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00349052

S. K. Lim, Physical design for 3D system on package, Design & Test of Computers, IEEE, vol.2211, pp.532-539, 2005.

N. Sherwani, Q. Yu, and S. Badida, Introduction To Multichip Modules Arteris white paper A Comparison of Network-on-Chip and Bussses AMBA Specification " , www.arm.com, 1999. [14] International Business Machines Corporation The CoreConnect? Bus Architecture ST-BUS Generic Device Specification, 1995.

E. Bong, J. , H. Wook, C. Neungsoo, P. et al., SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs Reducing the dynamic power and leakage power of a high performance SoC, Computational Science, International Conference on, vol.17, pp.244-251, 2006.

D. Gaoming, Z. Duoli, Y. Yongsheng, and M. Liang, LuoFeng Geng; YuKung Song; MingLun Gao FPGA prototype design of Network on Chips Anti-counterfeiting, Security and Identification, pp.348-351, 2008.

J. Hur, T. Stevanov, S. Wong, and S. Vassiliadis, Systematic Customization of On-Chip Crossbar Interconnects, pp.61-72, 2007.
DOI : 10.1007/978-3-540-71431-6_6

S. Murali, L. Benini, G. De-micheli, D. Micheli, and G. , An Application-Specific Design Methodology for On- Chip Crossbar Generation Computer-Aided Design of Integrated Circuits and Systems Introduction: The Network-on-Chip Paradigm in Practice and Research, IEEE Transactions IEEE Design and Test of Computers, vol.26, issue.22 5, pp.1283-1296, 2005.

W. J. Dally and B. Towles, Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), pp.684-689, 2001.
DOI : 10.1109/DAC.2001.935594

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.5322

M. Donno, A. Ivaldi, L. Benini, and E. Macii, Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation , DAC '03, p.622, 2003.
DOI : 10.1145/775832.775989

K. Srinivasan, K. S. Chatha, and G. Konjevod, Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms, 2007 Asia and South Pacific Design Automation Conference, pp.184-190, 2007.
DOI : 10.1109/ASPDAC.2007.357983

P. Frantz, A. Carro, L. Cota, E. Lima-kastensmidt, and F. , Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers, 12th IEEE International On-Line Testing Symposium (IOLTS'06), pp.191-192, 2006.
DOI : 10.1109/IOLTS.2006.33

Y. Yang, J. Yulu, Y. Ming, H. Mei, Y. Yingtao et al., Multi-path Routing for Mesh/Torus- Based NoCs, Fourth International Conference on, pp.734-742

P. Guerrier and A. Greiner, A generic architecture for on-chip packet-switched interconnections, Europe Conference and Exhibition, Proceedings, pp.250-256, 2000.

M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, and A. Scandurra, Spidergon: a novel onchip communication network, Proceedings. International Symposium on, pp.15-16, 2004.

B. S. Feero and E. G. Friedman, 3-D Topologies for Networks-on-Chip " , Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.1530, pp.1081-1090, 2007.

B. Feero, P. Pande, C. Kuei-chung, S. Jih-sheng, and C. Tien-fu, Performance Evaluation for Three-Dimensional Networks-On- Chip Evaluation and Design Trade-Offs Between Circuit-Switched and Packet-Switched NOCs for Application-Specific SOCs, Design Automation Conference Proceedings, pp.305-310, 2006.

A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini, Fault Tolerance Overhead in Network-on- Chip Flow Control Schemes, Integrated Circuits and Systems Design, 18th Symposium on, pp.224-229, 2005.

M. Palesi, R. Holsmark, S. Kumar, V. Catania, H. Barati et al., Application Specific Routing Algorithms for Networks on Chip Routing Algorithms Study and Comparing in Interconnection Networks, Information and Communication Technologies: From Theory to Applications, pp.316-3301, 2008.

D. Ianni and M. , Wormhole Deadlock Prediction, Proceedings of the Third International Euro- Par Conference on Parallel Processing, pp.188-195, 1997.

R. Holsmark, M. Palesi, and S. Kumar, Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006.
DOI : 10.1109/DSD.2006.36

G. Ascia, V. Catania, M. Palesi, and D. Patti, Neighbors-on-Path: A New Selection Strategy for On-Chip Networks, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, pp.79-84, 2006.
DOI : 10.1109/ESTMED.2006.321278

F. Moraes, N. Calazans, A. Mello, L. Moller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004.
DOI : 10.1016/j.vlsi.2004.03.003

P. Vivet, D. Lattard, F. Clermidy, E. Beigne, C. Bernard et al., FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications, 2007.

J. Hu and R. Marculescu, Smart routing for networks-on-chip, 2004.

D. Borrione, A. Helmy, L. Pierre, and J. Schmaltz, A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, First International Symposium on Networks-on-Chip (NOCS'07), pp.127-136, 2007.
DOI : 10.1109/NOCS.2007.1

URL : https://hal.archives-ouvertes.fr/hal-00156745

L. Se-joong, L. Kangmin, and Y. Hoi-jun, Analysis and Implementation of Practical, Cost-Effective Networks on Chips, IEEE Design and Test of Computers, vol.22, issue.5, pp.422-433, 2005.
DOI : 10.1109/MDT.2005.103

S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta et al., Designing Application-Specific Networks on Chips with Floorplan Information, Computer- Aided Design IEEE/ACM International Conference on, vol.44, pp.355-362, 2006.

P. Grosse1, L. Durand1, P. Feautrier, S. Rodriguez, and B. Jacob, Power Modeling of a NoC Based Design for High Speed Telecommunication Systems Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Energy/Power Breakdown of Pipelined Nanometer Caches (90nm, Low Power Electronics and Design, Proceedings of the 2006 International Symposium on, pp.157-16825, 2006.

R. Mullins, Minimizing Dynamic Power Consumption in On-Chip Networks, System-on- Chip, International Symposium on, pp.1-4

J. Chan and S. Parameswaran, Nocee : energy macro-model extraction methodology for network on chip routers, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp.254-259, 2005.
DOI : 10.1109/ICCAD.2005.1560073

M. Amde, T. Felicijan, A. Efthymiou, D. Edwards, and L. Lavagno, Asynchronous on-chip networks, Computers and Digital Techniques, IEE Proceedings, pp.273-283, 2005.
DOI : 10.1049/pbcs018e_ch18

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.675.50

T. Werner and V. Akella, Asynchronous processor survey, Computer, vol.30, issue.11, pp.67-76, 1997.
DOI : 10.1109/2.634866

E. Beigne, E. Clermidy, P. Vivet, A. Clouard, and M. Renaudin, An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005.
DOI : 10.1109/ASYNC.2005.10

URL : https://hal.archives-ouvertes.fr/hal-00009566

A. Sheibanyrad, Implémentation Asynchrone d'un Réseau-sur-Puce Distribué, pp.2008-53

E. Salminen, A. Kulmala, and T. D. Hamalainen, On network-on-chip comparison, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp.503-510, 2007.
DOI : 10.1109/DSD.2007.4341515

I. Cidon and I. Keidar, Zooming in on Network-on-Chip Architectures, 2005.
DOI : 10.1007/978-3-642-11476-2_1

T. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys, vol.38, issue.1, pp.1-51, 2006.
DOI : 10.1145/1132952.1132953

J. Delorme, Méthodologie de Modélisation et d'Exploration d'Architecture de Réseaux sur Puce Appliquée aux Telecommunications, 2007.

X. Li and O. Hammami, NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis, 2006 International Symposium on Industrial Embedded Systems, pp.1-4, 2006.
DOI : 10.1109/IES.2006.357469

C. Ciordas, A. Hansson, K. Goossens, T. Basten, K. Goossens et al., A Monitoring-Aware Network-on-Chip Design Flow AEthereal network on chip: concepts, architectures, and implementations A Low Cost Network-on-Chip with Guaranteed Service Well, Digital System Design: Architectures, Methods and Tools, 9th EUROMICRO Conference on Nano-Networks and Workshops, 1st International Conference on, pp.97-106, 2005.

E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, QNoC: QoS architecture and design process for network on chip, Special issue on networks on chip, Pages 105-128, 2004.
DOI : 10.1016/j.sysarc.2003.07.004

D. Bertozzi and L. Benini, Xpipes: a network-on-chip architecture for gigascale systems-onchip " , Circuits and Systems Magazine, pp.18-31, 2004.

S. Evain, J. Diguet, and D. Houzet, µspider: a CAD tool for efficient NoC design, Norchip Conference, pp.218-221, 2004.

D. N. Jayasimha, B. Zafar, and Y. Hoskote, On-Chip Interconnection Networks: Why They are Different and How to Compare Them

T. Marescaux, A. Rångevall, V. Nollet, A. Bartic, H. Corporaal et al., Distributed congestion control for packet switched networks on chip Automatic network generation for systemon-chip communication design, Parallel Computing Conference , In Proceedings, Malagà, Spain Hardware/Software Codesign and System SynthesisIFIP International Conference on, pp.255-260, 2005.

M. Moadeli, A. Shahrabi, W. Vanderbauwhede, and M. Ould-khaoua, An Analytical Performance Model for the Spidergon NoC, 21st International Conference on Advanced Networking and Applications (AINA '07), pp.1014-1021, 2007.
DOI : 10.1109/AINA.2007.31

S. Kambiz, A. Kahng, B. Li, and L. Peh, 0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration, Poster, GSRC Annual Symposium, vol.29, issue.2, 2008.

U. Y. Ogras, R. Marcillescu, H. Gyu, L. Choudhary, P. Marculescu et al., Challenges and Promising Results in NoC Prototyping Using FPGAs Design space exploration and prototyping for on-chip multimedia applications, Micro, IEEE Design Automation Conference73] Xilinx Chipscope Pro, pp.86-95137, 2006.

K. Goossens, A. Radulescu, A. Hansson, A. Hansson, M. Wiggers et al., A unified approach to constrained mapping and routing on network-on-chip architectures Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip, Hardware/Software Codesign and System Synthesis Second ACM/IEEE International Symposium on, pp.75-80211, 2005.

S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De-micheli, A Methodology for Mapping Multiple Use-Cases onto Networks on Chips, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006.
DOI : 10.1109/DATE.2006.244007

G. Ascia, V. Catania, and M. Palesi, Multi-objective mapping for mesh-based NoC architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.182-187, 2004.
DOI : 10.1145/1016720.1016765

C. Ciordas, K. Goossens, A. Radulescu, and T. Basten, NoC Monitoring: Impact on the Design Flow, 2006 IEEE International Symposium on Circuits and Systems, 1984.
DOI : 10.1109/ISCAS.2006.1693001

J. E. Becker, C. Bieser, J. Becker, and K. Mueller-glase, Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System, 2006 IEEE International Symposium on Industrial Electronics, pp.3184-3189, 2006.
DOI : 10.1109/ISIE.2006.296126

V. Soteriou, W. Hangsheng, and L. Peh, A Statistical Traffic Model for On-Chip Interconnection Networks, 14th IEEE International Symposium on Modeling, Analysis, and Simulation, pp.104-116, 2006.
DOI : 10.1109/MASCOTS.2006.9

A. Scherrer, A. Fraboulet, and T. Risset, Long-Range Dependence and On-chip Processor Traffic Linear Feedback Shift Register, Microprocessors and Microsystems, pp.72-80, 2009.
DOI : 10.1016/j.micpro.2008.08.010

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.405.3452

N. Genko, D. Atienza, D. Micheli, G. Mendias, J. M. Hermida et al., A Complete Network-On-Chip Emulation Framework, Design, Automation and Test in Europe, pp.246-251, 2005.
DOI : 10.1109/DATE.2005.5

URL : https://hal.archives-ouvertes.fr/hal-00181642

B. Sethuraman and R. Vemuri, optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs, Proceedings of the Design Automation & Test in Europe Conference, pp.6-10, 2006.
DOI : 10.1109/DATE.2006.243837

R. Gindin, I. Cidon, and I. Keidar, NoC-Based FPGA: Architecture and Routing, First International Symposium on Networks-on-Chip (NOCS'07), pp.253-264, 2007.
DOI : 10.1109/NOCS.2007.31

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.9731

J. Babb, R. Tessier, M. Dahl, S. Z. Hanono, D. M. Hoki et al., Logic emulation with virtual wires, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, issue.6, pp.609-626, 1997.
DOI : 10.1109/43.640619

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.17.9545

M. Rosemary and W. Simon, The ACM Robust Taboo Search (TS) for the Quadratic Assignment Problem METIS - Family of Multilevel Partitioning Algorithms Xilinx Virtex II Pro datasheet, Proceedings PowerPC 405 Embedded CoresPowerPC_405_Embedded_Cores [99] " MicroBlaze Processor RocketIO? Transceiver Characterization Report for Virtex-II Pro? X FPGA " www.xilinx.com, pp.285-285, 2009.

A. Fraboulet, T. Risset, and A. Scherrer, Cycle Accurate Simulation Model Generation for SoC Prototyping, p.18
DOI : 10.1007/978-3-540-27776-7_47

URL : https://hal.archives-ouvertes.fr/hal-00399647

S. Riso, G. Sassatelli, L. Torres, M. Robert, and F. G. Moraes, Réseau d'Interconnexion pour les Systèmes sur Puce, Signal Circuit and Systems ,IEEE International Conference on, pp.634-638, 2004.

S. Murali, C. Seiculescu, L. Benini, D. Micheli, and G. , Synthesis of networks on chips for 3D systems on chips Flow control Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip, Design Automation Conference Asia and South Pacific, In Proceedings and Distributed Processing and Applications, In Procedings, pp.242-247, 2007.

M. I. Panades and A. Greiner, Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures, First International Symposium on Networks-on-Chip (NOCS'07), pp.83-94, 2007.
DOI : 10.1109/NOCS.2007.14