Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform, Liste des Publications Publication internationales Digital System Design Architectures, Methods and Tools, pp.3-9, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00349055
Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor Prototyping: New Challenges for Embedded Software Designers RSP '08. The 19th IEEE, Rapid System PrototypingIFIP International Symposium on, pp.41-47, 2008. ,
DOI : 10.1109/rsp.2008.27
Networks-In-Package: Performances management and design methodology, VLSI-DAT 2008. IEEE International Symposium on, pp.140-143, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00349052
Scalable Multi-FPGA Platform for Networks-On- Chip Emulation, Application -specific Systems, Architectures and Processors, 2007. ASAP. IEEE International Conf. on, pp.54-60, 2007. ,
URL : https://hal.archives-ouvertes.fr/hal-00264982
From Networks-On-Chip Emulation to Networks-In-Package Synthesis, French Winter School on Heterogeneous Embedded Systems Design, pp.7-9, 2008. ,
Flexible Architectures for HW/SW Interfaces " French Winter School on Heterogeneous Embedded Systems Design, Villard-de, 2007. ,
Networks on chip: a new paradigm for systems on chip design, Europe Conference and Exhibition, 2002. Proceedings, pp.418-419, 2002. ,
Design space exploration for hardware/software codesign of multiprocessor systems, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2000. ,
DOI : 10.1109/IWRSP.2000.854975
URL : https://hal.archives-ouvertes.fr/hal-00008096
Design Space Exploration for Optimizing On-Chip Communication Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23, issue.6, pp.952-961, 2004. ,
DOI : 10.1109/TCAD.2004.828127
Formal methods for networks on chips Application of Concurrency to System Design, Fifth International Conference on, pp.188-189, 2005. ,
Key research problems in NoC design: a holistic perspective, Hardware/Software Codesign and System Synthesis Third IEEE/ACM/IFIP International Conference on, pp.69-74, 2005. ,
Large Tandem Queueing Networks with Blocking Queueing Systems: Theory and Applications, v.41 n.1-2, Interopérabilité en Emulation et Prototypage Matériel, pp.45-72, 2002. ,
Networks-In-Package: Performances management and design methodology, IEEE International Symposium on, pp.140-143, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00349052
Physical design for 3D system on package, Design & Test of Computers, IEEE, vol.2211, pp.532-539, 2005. ,
Introduction To Multichip Modules Arteris white paper A Comparison of Network-on-Chip and Bussses AMBA Specification " , www.arm.com, 1999. [14] International Business Machines Corporation The CoreConnect? Bus Architecture ST-BUS Generic Device Specification, 1995. ,
SONA: An On-Chip Network for Scalable Interconnection of AMBA-Based IPs Reducing the dynamic power and leakage power of a high performance SoC, Computational Science, International Conference on, vol.17, pp.244-251, 2006. ,
LuoFeng Geng; YuKung Song; MingLun Gao FPGA prototype design of Network on Chips Anti-counterfeiting, Security and Identification, pp.348-351, 2008. ,
Systematic Customization of On-Chip Crossbar Interconnects, pp.61-72, 2007. ,
DOI : 10.1007/978-3-540-71431-6_6
An Application-Specific Design Methodology for On- Chip Crossbar Generation Computer-Aided Design of Integrated Circuits and Systems Introduction: The Network-on-Chip Paradigm in Practice and Research, IEEE Transactions IEEE Design and Test of Computers, vol.26, issue.22 5, pp.1283-1296, 2005. ,
Route packets, not wires: on-chip interconnection networks, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), pp.684-689, 2001. ,
DOI : 10.1109/DAC.2001.935594
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1.5322
Clock-tree power optimization based on RTL clock-gating, Proceedings of the 40th conference on Design automation , DAC '03, p.622, 2003. ,
DOI : 10.1145/775832.775989
Application Specific Network-on-Chip Design with Guaranteed Quality Approximation Algorithms, 2007 Asia and South Pacific Design Automation Conference, pp.184-190, 2007. ,
DOI : 10.1109/ASPDAC.2007.357983
Evaluating SEU and Crosstalk Effects in Network-on-Chip Routers, 12th IEEE International On-Line Testing Symposium (IOLTS'06), pp.191-192, 2006. ,
DOI : 10.1109/IOLTS.2006.33
Multi-path Routing for Mesh/Torus- Based NoCs, Fourth International Conference on, pp.734-742 ,
A generic architecture for on-chip packet-switched interconnections, Europe Conference and Exhibition, Proceedings, pp.250-256, 2000. ,
Spidergon: a novel onchip communication network, Proceedings. International Symposium on, pp.15-16, 2004. ,
3-D Topologies for Networks-on-Chip " , Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.1530, pp.1081-1090, 2007. ,
Performance Evaluation for Three-Dimensional Networks-On- Chip Evaluation and Design Trade-Offs Between Circuit-Switched and Packet-Switched NOCs for Application-Specific SOCs, Design Automation Conference Proceedings, pp.305-310, 2006. ,
Fault Tolerance Overhead in Network-on- Chip Flow Control Schemes, Integrated Circuits and Systems Design, 18th Symposium on, pp.224-229, 2005. ,
Application Specific Routing Algorithms for Networks on Chip Routing Algorithms Study and Comparing in Interconnection Networks, Information and Communication Technologies: From Theory to Applications, pp.316-3301, 2008. ,
Wormhole Deadlock Prediction, Proceedings of the Third International Euro- Par Conference on Parallel Processing, pp.188-195, 1997. ,
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions, 9th EUROMICRO Conference on Digital System Design (DSD'06), 2006. ,
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Neighbors-on-Path: A New Selection Strategy for On-Chip Networks, 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia, pp.79-84, 2006. ,
DOI : 10.1109/ESTMED.2006.321278
HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, vol.38, issue.1, pp.69-93, 2004. ,
DOI : 10.1016/j.vlsi.2004.03.003
FAUST, an Asynchronous Network-on-Chip based Architecture for Telecom Applications, 2007. ,
Smart routing for networks-on-chip, 2004. ,
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study, First International Symposium on Networks-on-Chip (NOCS'07), pp.127-136, 2007. ,
DOI : 10.1109/NOCS.2007.1
URL : https://hal.archives-ouvertes.fr/hal-00156745
Analysis and Implementation of Practical, Cost-Effective Networks on Chips, IEEE Design and Test of Computers, vol.22, issue.5, pp.422-433, 2005. ,
DOI : 10.1109/MDT.2005.103
Designing Application-Specific Networks on Chips with Floorplan Information, Computer- Aided Design IEEE/ACM International Conference on, vol.44, pp.355-362, 2006. ,
Power Modeling of a NoC Based Design for High Speed Telecommunication Systems Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation Energy/Power Breakdown of Pipelined Nanometer Caches (90nm, Low Power Electronics and Design, Proceedings of the 2006 International Symposium on, pp.157-16825, 2006. ,
Minimizing Dynamic Power Consumption in On-Chip Networks, System-on- Chip, International Symposium on, pp.1-4 ,
Nocee : energy macro-model extraction methodology for network on chip routers, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pp.254-259, 2005. ,
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Asynchronous on-chip networks, Computers and Digital Techniques, IEE Proceedings, pp.273-283, 2005. ,
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URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.675.50
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An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework, 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005. ,
DOI : 10.1109/ASYNC.2005.10
URL : https://hal.archives-ouvertes.fr/hal-00009566
Implémentation Asynchrone d'un Réseau-sur-Puce Distribué, pp.2008-53 ,
On network-on-chip comparison, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), pp.503-510, 2007. ,
DOI : 10.1109/DSD.2007.4341515
Zooming in on Network-on-Chip Architectures, 2005. ,
DOI : 10.1007/978-3-642-11476-2_1
A survey of research and practices of Network-on-chip, ACM Computing Surveys, vol.38, issue.1, pp.1-51, 2006. ,
DOI : 10.1145/1132952.1132953
Méthodologie de Modélisation et d'Exploration d'Architecture de Réseaux sur Puce Appliquée aux Telecommunications, 2007. ,
NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis, 2006 International Symposium on Industrial Embedded Systems, pp.1-4, 2006. ,
DOI : 10.1109/IES.2006.357469
A Monitoring-Aware Network-on-Chip Design Flow AEthereal network on chip: concepts, architectures, and implementations A Low Cost Network-on-Chip with Guaranteed Service Well, Digital System Design: Architectures, Methods and Tools, 9th EUROMICRO Conference on Nano-Networks and Workshops, 1st International Conference on, pp.97-106, 2005. ,
QNoC: QoS architecture and design process for network on chip, Special issue on networks on chip, Pages 105-128, 2004. ,
DOI : 10.1016/j.sysarc.2003.07.004
Xpipes: a network-on-chip architecture for gigascale systems-onchip " , Circuits and Systems Magazine, pp.18-31, 2004. ,
µspider: a CAD tool for efficient NoC design, Norchip Conference, pp.218-221, 2004. ,
On-Chip Interconnection Networks: Why They are Different and How to Compare Them ,
Distributed congestion control for packet switched networks on chip Automatic network generation for systemon-chip communication design, Parallel Computing Conference , In Proceedings, Malagà, Spain Hardware/Software Codesign and System SynthesisIFIP International Conference on, pp.255-260, 2005. ,
An Analytical Performance Model for the Spidergon NoC, 21st International Conference on Advanced Networking and Applications (AINA '07), pp.1014-1021, 2007. ,
DOI : 10.1109/AINA.2007.31
0: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration, Poster, GSRC Annual Symposium, vol.29, issue.2, 2008. ,
Challenges and Promising Results in NoC Prototyping Using FPGAs Design space exploration and prototyping for on-chip multimedia applications, Micro, IEEE Design Automation Conference73] Xilinx Chipscope Pro, pp.86-95137, 2006. ,
A unified approach to constrained mapping and routing on network-on-chip architectures Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip, Hardware/Software Codesign and System Synthesis Second ACM/IEEE International Symposium on, pp.75-80211, 2005. ,
A Methodology for Mapping Multiple Use-Cases onto Networks on Chips, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006. ,
DOI : 10.1109/DATE.2006.244007
Multi-objective mapping for mesh-based NoC architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.182-187, 2004. ,
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NoC Monitoring: Impact on the Design Flow, 2006 IEEE International Symposium on Circuits and Systems, 1984. ,
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Evaluation of a Packet Switching Algorithm for Network on Chip Topologies using a Xilinx Virtex-II FPGA based Rapid Prototyping System, 2006 IEEE International Symposium on Industrial Electronics, pp.3184-3189, 2006. ,
DOI : 10.1109/ISIE.2006.296126
A Statistical Traffic Model for On-Chip Interconnection Networks, 14th IEEE International Symposium on Modeling, Analysis, and Simulation, pp.104-116, 2006. ,
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Long-Range Dependence and On-chip Processor Traffic Linear Feedback Shift Register, Microprocessors and Microsystems, pp.72-80, 2009. ,
DOI : 10.1016/j.micpro.2008.08.010
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.405.3452
A Complete Network-On-Chip Emulation Framework, Design, Automation and Test in Europe, pp.246-251, 2005. ,
DOI : 10.1109/DATE.2005.5
URL : https://hal.archives-ouvertes.fr/hal-00181642
optiMap: a tool for automated generation of NoC architectures using multi-port routers for FPGAs, Proceedings of the Design Automation & Test in Europe Conference, pp.6-10, 2006. ,
DOI : 10.1109/DATE.2006.243837
NoC-Based FPGA: Architecture and Routing, First International Symposium on Networks-on-Chip (NOCS'07), pp.253-264, 2007. ,
DOI : 10.1109/NOCS.2007.31
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.62.9731
Logic emulation with virtual wires, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, issue.6, pp.609-626, 1997. ,
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The ACM Robust Taboo Search (TS) for the Quadratic Assignment Problem METIS - Family of Multilevel Partitioning Algorithms Xilinx Virtex II Pro datasheet, Proceedings PowerPC 405 Embedded CoresPowerPC_405_Embedded_Cores [99] " MicroBlaze Processor RocketIO? Transceiver Characterization Report for Virtex-II Pro? X FPGA " www.xilinx.com, pp.285-285, 2009. ,
Cycle Accurate Simulation Model Generation for SoC Prototyping, p.18 ,
DOI : 10.1007/978-3-540-27776-7_47
URL : https://hal.archives-ouvertes.fr/hal-00399647
Réseau d'Interconnexion pour les Systèmes sur Puce, Signal Circuit and Systems ,IEEE International Conference on, pp.634-638, 2004. ,
Synthesis of networks on chips for 3D systems on chips Flow control Performance and Complexity Analysis of Credit-Based End-to-End Flow Control in Network-on-Chip, Design Automation Conference Asia and South Pacific, In Proceedings and Distributed Processing and Applications, In Procedings, pp.242-247, 2007. ,
Bi-Synchronous FIFO for Synchronous Circuit Communication Well Suited for Network-on-Chip in GALS Architectures, First International Symposium on Networks-on-Chip (NOCS'07), pp.83-94, 2007. ,
DOI : 10.1109/NOCS.2007.14