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Architectures Flexibles pour la Validation et L'exploration de Réseaux-sur-Puce

Abstract : For A multiprocessor system-on-chip (MPSOC), the communication backbone is a central component of prime importance. This is due to the importance of the communications on such distributed systems. Now that networks-on-chip (NoCs) are admitted to be the solution which theoretically best solves the problem of on-chip communications, an important problem which rises consists in providing the designer with fast validation techniques able to tackle such complexes systems. Indeed, despite their regular architectures networks-in-chip internal interactions are difficult to formalize. On the other side, classical validation approaches are far from being suited for NoC-based systems due to their lack of flexibility and scalability. This thesis introduces a new concept in the field of hardware validation of networkson- chip; we have called this new concept “Inaccurate Hardware Emulation” in contrast with most hardware emulation approaches which assume a “cycle accurate bit accurate” precision. Our approach inherits from all advantages of hardware prototyping on reconfigurable devices and adds new scalability features. Study conducted during this thesis showed that under the non-congested regime a NoC may admit a number of alterations on its characteristics (introduced by the emulation platform) without adopting a completely different behavior. The multi-FPGA emulation technique proposed in this thesis is highly flexible since it relies on serial inter-FPGA interconnections. Serial interconnections are less sensitive to noises than parallel style of interconnections, and allow then for higher transfer rates. On the other hand, our emulation approaches does not poses any constraint on the emulation speed. If we consider the fact that serial interconnection schemes may introduce additional delays and the high speeds of the emulation process, performance of the NoC being emulated on the multi-FPGA emulator may deviate from the original NoC. We have studied this phenomenon and we have proposed various solutions for it.
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Submitted on : Friday, November 13, 2009 - 10:35:27 AM
Last modification on : Friday, December 11, 2020 - 8:28:03 AM
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  • HAL Id : tel-00431799, version 1




A. Kouadri-Mostefaoui. Architectures Flexibles pour la Validation et L'exploration de Réseaux-sur-Puce. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2009. Français. ⟨tel-00431799⟩



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