Skip to Main content Skip to Navigation

Modélisation et Simulation Rapide au niveau cycle pour l'Exploration Architecturale de Systèmes Intégrés sur puce

Richard Buchmann 1
1 ALSOC - Architecture et Logiciels pour Systèmes Embarqués sur Puce
LIP6 - Laboratoire d'Informatique de Paris 6
Abstract : System On Chip modeling is based on software specification, hardware modeling, and software to hardware mapping. The system designer goal is to find the best mapping that matches specifications while optimizing performances, silicium area, and energy consumption. The same system designer is faced with architectural exploration issues due to the important number hardware/software parameters. Architectural exploration is time consuming, and any tool that can reduce or ease the development process is of paramount interest. This thesis presents principles and tools to facilitate hardware development and to speedup synchronous hardware simulation. The targeted simulation platform is based on SystemC language and relies on bit/cycle accurate models. Four chapters present: • The use of communicating synchronous finite state machines as an effective means to model hardware components and platform (CFSM) ; • SystemC model generation from synthesizable VHDL description at RTL level ; • Writing rules checking of SystemC models ; • Fast simulation using entirely static scheduling. These tools allow the system designer to build an hardware architecture using synthesizable components at RTL level, and SystemC components, based on CFSM model. SystemCASS simulates such architecture 12 faster than a simulator using a dynamic scheduling.
Complete list of metadatas

Cited literature [36 references]  Display  Hide  Download
Contributor : Richard Buchmann <>
Submitted on : Friday, October 23, 2009 - 2:30:53 PM
Last modification on : Friday, January 8, 2021 - 5:32:08 PM
Long-term archiving on: : Thursday, June 17, 2010 - 5:45:25 PM


  • HAL Id : tel-00426066, version 1


Richard Buchmann. Modélisation et Simulation Rapide au niveau cycle pour l'Exploration Architecturale de Systèmes Intégrés sur puce. Micro et nanotechnologies/Microélectronique. Université Pierre et Marie Curie - Paris VI, 2006. Français. ⟨tel-00426066⟩



Record views


Files downloads