158 IV.2.1.1.A Influence de l'épaisseur de l'oxyde tunnel, p.164 ,
Flash Memories, 1999. ,
The numerical simulation of substrate and gate currents in MOS and EPROMs, Proceedings of International Electron Devices Meeting, p.289, 1995. ,
DOI : 10.1109/IEDM.1995.499198
Hot-electron emission in N-channel IGFET's, IEEE Transactions on Electron Devices, vol.26, issue.4, pp.520-532, 1979. ,
DOI : 10.1109/T-ED.1979.19456
Investigation of charging/discharging phenomena in nano-crystal memories, Superlatt. Microstruct, vol.28, pp.5-6, 2000. ,
Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices, IEEE Transactions on Electron Devices, vol.48, issue.8, p.1789, 2001. ,
DOI : 10.1109/16.936709
Etude du transport électrique et de la fiabilité des isolants des mémoires non volatiles à grille flottante, Thèse de doctorat INPG, 1999. ,
Performance, Degradation Monitors, and Reliability of the CHISEL Injection Regime, IEEE Transactions on Device and Materials Reliability, vol.4, issue.3, p.327, 2004. ,
DOI : 10.1109/TDMR.2004.837208
Efficient non-local modelling of the electron energy distribution in sub-micron MOSFET's, IEDM Tech. Dig, p.451, 1990. ,
Simple and efficient modeling of EPROM writing, IEEE Transactions on Electron Devices, vol.38, issue.3, pp.603-610 ,
DOI : 10.1109/16.75172
Charge transport and storage in metal-nitride-oxide-silicon (MNOS) structures, J. Appl. Phys, vol.408, issue.8, p.3307, 1969. ,
Quantum Physics, 1995. ,
Basics of nonvolatile semiconductor memory devices, NVSM Technology, 1998. ,
Fowler???Nordheim conduction in polysilicon (n+)-oxide???silicon (p) structures: Limit of the classical treatment in the barrier height determination, Journal of Applied Physics, vol.89, issue.12, pp.7994-8001, 2001. ,
DOI : 10.1063/1.1374479
Modeling and simulation of electron injection during programming in Twin Flash/spl trade/ devices based on energy transport and the non-local lucky electron concept, Electrical Performance of Electronic Packaging IWCE-04, pp.239-242, 2004. ,
DOI : 10.1109/IWCE.2004.1407373
Monte Carlo Simulation of Charge Carrier Injection in Twin Flash Memory Devices during Program and Erase, 2006 International Conference on Simulation of Semiconductor Processes and Devices, pp.322-325, 2006. ,
DOI : 10.1109/SISPAD.2006.282900
Lucky-electron model for channel hot-electron emission, IEDM Tech. Dig, p.22, 1979. ,
Monte Carlo Simulation of Program and Erase Charge Distributions in NROM(TM) Devices, 32nd European Solid-State Device Research Conference, p.187, 2002. ,
DOI : 10.1109/ESSDERC.2002.194901
Investigation of the influence of impact ionization feedback on the spatial distribution of hot carriers in a nMOSFET, Proc. of ESSDRC, 1997. ,
The origin of secondary electron gate current: A multiple stage Monte Carlo study for scaled, low power flash memory, IEDM Tech. Dig, p.889, 1998. ,
Quantum mechanics: non-relativistic theory, 1965. ,
Electrodynamics of Continuous Media, 1984. ,
A new analytical model of Channel Hot Electron (CHE) and Channel Initiated Secondary Electron (CHISEL) current suitable for compact modelling, International Conference on Modeling and Simulation of Microsystems Tech. Proc, 2002. ,
layer, Journal of Applied Physics, vol.75, issue.7, pp.3530-3535, 1994. ,
DOI : 10.1063/1.356116
The Theory of Electrical Conduction and Breakdown in Solids Dielectric, 1973. ,
Subthreshold behavior of dual-bit nonvolatile memories with very small regions of trapped charge, IEEE Transactions On Nanotechnology, vol.5, issue.4, p.373, 2006. ,
DOI : 10.1109/TNANO.2006.876920
« Model for drain current RTS amplitude in small area MOS transistors », Solid State Elec, p.1273, 1992. ,
Ultra thin silicon dioxide leakage current and scaling limit, Symp. VLSI Technol, pp.18-19, 1992. ,
MINIMOS - A Two-Dimensional MOS Transistor Analyzer, IEEE Journal of Solid-State Circuits, vol.15, issue.4, pp.27-1540, 1980. ,
DOI : 10.1109/JSSC.1980.1051444
Analysis and Simulation of Semiconductor Devices, 1984. ,
DOI : 10.1007/978-3-7091-8752-4
Problems related to p-n junctions in silicon, Solid-State Electronics, vol.2, issue.1, p.35, 1961. ,
DOI : 10.1016/0038-1101(61)90054-5
Diffusion of Hot and Cold Electrons in Semiconductor Barriers, Physical Review, vol.126, issue.6, 1962. ,
DOI : 10.1103/PhysRev.126.2002
Tunneling in Schottky barrier rectifiers " , Tunneling Phenomena in Solids, pp.105-125, 1969. ,
Lucky-electron model of channel hot-electron injection in MOSFET's, IEEE Trans. Electron Devices, issue.9, p.31, 1984. ,
Quantitative Model for Data Retention Loss at NROM Nitride Charge Trapping Devices after Program / Erase Cycling, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop, pp.78-80, 2006. ,
DOI : 10.1109/.2006.1629503
Tunneling in a finite superlattice, Applied Physics Letters, vol.22, issue.11, pp.562-564, 1973. ,
DOI : 10.1063/1.1654509
Guillaumot « Experimental and theoretical investigation of nanocrystals and nitride-trap memory devices, IEEE Trans. On El. Dev, vol.48, issue.8, p.1789, 2001. ,
Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly, IEEE International Electron Devices Meeting 2003, p.541, 2003. ,
DOI : 10.1109/IEDM.2003.1269340
Metal nanocrystal memories. I. Device design and fabrication, IEEE Transactions on Electron Devices, vol.49, issue.9, p.1606, 2002. ,
DOI : 10.1109/TED.2002.802617
Metal nanocrystal memories-part II: electrical characteristics, IEEE Transactions on Electron Devices, vol.49, issue.9, p.1614, 2002. ,
DOI : 10.1109/TED.2002.802618
Subthreshold behavior of dual-bit nonvolatile memories with very small regions of trapped charge, IEEE Transactions On Nanotechnology, vol.5, issue.4, p.373203, 2006. ,
DOI : 10.1109/TNANO.2006.876920
Impact of few electron phenomena on floating-gate memory reliability, IEEE IEDM, pp.877-880, 2004. ,
Modeling of a Double-Gate FinFlash memory, ICMTD (International Conference on Memory Technology and Design), pp.153-156, 2005. ,
TCAD Modeling and Data of NOR Nanocrystal Memories, 2006 7th Annual Non-Volatile Memory Technology Symposium, pp.31-33, 2006. ,
DOI : 10.1109/NVMT.2006.378871
On the localization of the trapped charges in Silicon nanocrystal NOR Flash devices, Proc. of ICMTD, pp.247-250, 2007. ,
Investigation of Reliability Characteristics of Si Nanocrystal NOR Memory Arrays, NVSMW (Non Volatile Semiconductor Memory Workshop), pp.71-72, 2007. ,
Integration of CVD silicon nanocrystals in a 32Mb NOR flash memory, ESSDERC 2007, 37th European Solid State Device Research Conference, pp.410-413, 2007. ,
DOI : 10.1109/ESSDERC.2007.4430965
Integration of CVD Silicon Nanocrystals in a 32Mb NOR Flash Memory, papier ESSDERC sélectionné pour un article dans Solid-State Electronics : accepté ,