. Dans-un-deuxième-temps, il serait pertinent de prouver formellement que cette méthode de présynthèse (i.e. grammaire attribuée et optimisation) préserve la sémantique de la structure de choix initiale et que les ensembles d'équations logiques obtenues

}. Andriahantenaina and A. Greiner, Micro-network for SoC: implementation of a 32-port SPIN network, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.1128-1129, 2003.
DOI : 10.1109/DATE.2003.1253766

A. Alexandrescu, Modern C++ Design: Generic Programming and Design Patterns Applied. C++ in Depth Series, 2001.

A. Austern, Generic Programming and the STL: Using and Extending the C++ Standard Template Library, 1998.

A. Austern, The Standard Librarian: Defining Iterators and Const Iterators QNoC: QoS architecture and design process for network on chip, C/C++ Users Journal Journal of Systems Architecture, vol.19, issue.502-3, pp.74-79105, 2001.

E. Beigne, F. Clermidy, P. Vivet, and A. Clouard, Renaudin: An Asynchronous NOC Architecture Providing Low Latency Service and its Multi-Level Design Framework, ASYNC'05: Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems, pp.54-63, 2005.

S. [. Bainbridge and . Furber, Delay insensitive system-on-chip interconnect using 1-of-4 data encoding, Proceedings Seventh International Symposium on Asynchronous Circuits and Systems. ASYNC 2001, pp.118-126, 2001.
DOI : 10.1109/ASYNC.2001.914075

[. Bainbridge and S. Furber, Chain: a delay-insensitive chip area interconnect, IEEE Micro, vol.22, issue.5, pp.16-23, 2002.
DOI : 10.1109/MM.2002.1044296

D. and R. P. Plads, The VLSI-programming language Tangram and its translation into handshake circuits, Thèse de doctorat DK-2800 Kgs. Lyngby EDAC'91: Proceedings of the European Conference on Design Automation, pp.384-389, 1991.

M. Steven, A. J. Burns, and . Martin, Syntax-directed Translation of Concurrent Programs into Self-Timed Circuits, Proceedings of the fifth MIT conference on Advanced research in VLSI, pp.35-50, 1988.

M. Steven, A. J. Burns, and . Martin, Synthesis of Self-Timed Circuits by Program Transformation (éditeur): The Fusion of Hardware Design and Verification, pp.99-116, 1988.

[. Benini and G. D. Micheli, Networks on chips: a new SoC paradigm, Computer, vol.35, issue.1, pp.70-78, 2002.
DOI : 10.1109/2.976921

[. Bjerregaard and S. Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys, vol.38, issue.1, pp.1-51, 2006.
DOI : 10.1145/1132952.1132953

[. Bjerregaard, S. Mahadevan, R. Grøndahl-olsen, and J. Sparsø, An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip, 2005 International Symposium on System-on-Chip, pp.171-174, 2005.
DOI : 10.1109/ISSOC.2005.1595670

[. Bjerregaard, S. Mahadevan, and J. Sparsø, A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modelling, PATMOS'04: Proceedings of the 14th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.301-310, 2004.

[. Bregier, Synthèse automatisée de circuits asynchrones optimisés prouvés Quasi Insensibles aux Délais, Thèse de doctorat, Institut National Polytechnique de Grenoble (INPG), 2007.

[. Bjerregaard and J. Sparsø, Virtual channel designs for guaranteeing bandwidth in asynchronous network-on-chip, Proceedings Norchip Conference, 2004., pp.269-272, 2004.
DOI : 10.1109/NORCHP.2004.1423875

[. Bjerregaard and J. Sparsø, A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip, Design, Automation and Test in Europe
DOI : 10.1109/DATE.2005.36

URL : https://hal.archives-ouvertes.fr/hal-00181298

[. Bjerregaard, J. Sparsøbv06, and ]. E. Beigné, Vivet: Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture Timing Analysis for Extended Burst-Mode Circuits, Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC'06: Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems ASYNC'03: Proceedings of the 3rd IEEE International Symposium on Asynchronous Circuits and Systems, pp.34-43, 1997.

L. Cai and D. Gajski, Transaction Level Modeling: An Overview, Proceedings of the 1st IEEEIFIP International Conference on Hardware/Software Codesign and System Synthesis Cidon et Idit Keidar: Zooming in on Network-on-Chip Architectures. rapport technique, pp.19-24, 2003.

J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Y. et al., Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers, Spidergon: a novel on-chip communication network, pp.80-315, 1997.

J. Thomas, C. E. Chaney, and . Molnar, Anomalous Behavior of Synchronizer and Arbiter Circuits [Cor94] Henk Corporaal: Design of Transport Triggered Architectures, GLSV'94: Proceedings of the 4th Great Lakes Symposium on VLSI, pp.421-422, 1973.

W. J. Dally, Virtual-channel flow control, IEEE Transactions on Parallel and Distributed Systems, vol.3, issue.2, pp.194-205, 1992.
DOI : 10.1109/71.127260

[. Durand, C. Bernard, and D. Lattard, FAUST: On-Chip Distributed SoC Architecture for a 4G Baseband Modem Chipset, Proc. Design and Reuse IP-SOC, pp.51-55, 2005.

A. Vu-dinh-duc, P. Vivet, and A. Clouard, A Transaction Level Modeling of Network-on-Chip Architecture for Energy Estimation, 2007 IEEE International Conference on Research, Innovation and Vision for the Future, pp.58-64, 2007.
DOI : 10.1109/RIVF.2007.369136

J. William, C. L. Dally, and . Seitz, Deadlock-Free Message Routing in Multiprocessor Interconnection Networks, Computers, IEEE Transactions on Computers, issue.5, pp.36547-553, 1987.

J. William, B. Dally, and . Towles, Route Packets, Not Wires: On-Chip Inteconnection Networks, Proceedings of the 38th conference on Design automation, pp.684-689, 2001.

J. Duato, S. Yalamanchili, and N. Lionel, INTERCONNECTION NETWORKS: AN ENGINEERING APPROACH, 2002.

R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin et al., MINIMALIST: An environment for the synthesis, verification and testability of burst-mode asynchronous machines, 1999.

[. Folco, Contribution à la synthèse des circuits asynchrones Quasi Insensibles aux Délais, applications aux systèmes sécurisés, Thèse de doctorat , Institut National Polytechnique de Grenoble (INPG), 2007.

P. Guerrier and A. Greiner, A Generic Architecture for On-Chip Packet-Switched Interconnections, Proceedings of the conference on Design, automation and test in Europe, pp.250-256, 2000.

[. Modeling and . Sys-temc, TLM Concepts and Applications for Embedded Systems, 2006.

[. Gamma, R. Helm, R. Johnson, and J. Vlissides, Design Patterns: Elements of Reusable Object-Oriented Software [Gin03] Ran Ginosar: Fourteen Ways to Fool Your Synchronizer, ASYNC'03: Proceedings of the 9th IEEE International Symposium on Asynchronous Circuits and Systems, pp.89-96, 1995.

J. Christopher, L. M. Glass, and . Ni, The turn model for adaptive routing, International Symposium on Computer Architecture, pp.278-287, 1992.

C. Helmstetter, Validation de Modèles de Systèmes sur Puce en Présence d'Ordonnancements Indéterministes et de Temps Imprécis, Thèse de doctorat, Institut National Polytechnique de Grenoble (INPG), 2007.

C. Helmstetter, F. Maraninchi, L. Maillet-contoz, and M. Moy, Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip. Dans FMCAD'06: Formal Methods in Computer-Aided Design, pp.171-178, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00311006

]. C. Hoa78 and . Hoare, Communicating Sequential Processes, Commununications of the ACM, vol.21, issue.8, pp.666-677, 1978.

C. Koch-hofer, M. Renaudin, Y. Thonnart, and P. Vivet, ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC, First International Symposium on Networks-on-Chip (NOCS'07), pp.295-306, 2007.
DOI : 10.1109/NOCS.2007.12

A. Tareq-hasan-khan and . Habibi, Sofiène Tahar et Otmane Ait Mohamed: Automatic Generation of Transactors in SystemC, FDL'07: Proceedings of the 9th Forum on specification and Design Languages, 2007.

J. David and . Kinniment, Synchronization and Arbitration in Digital Systems

[. Karim, A. Nguyen, and S. Dey, An interconnect architecture for networking systems on chips, IEEE Micro, vol.22, issue.5, pp.36-45, 2002.
DOI : 10.1109/MM.2002.1044298

[. Karim, A. Nguyen, S. Dey, and R. Rao, On-chip communication architecture for OC-768 network processors, Proceedings of the 38th conference on Design automation , DAC '01, pp.678-683, 2001.
DOI : 10.1145/378239.379047

L. Lamport, Time, clocks, and the ordering of events in a distributed system, Communications of the ACM, vol.21, issue.7, pp.558-565, 1978.
DOI : 10.1145/359545.359563

A. J. Martin, The Probe: An Addition to Communication Primitives Rapport technique CaltechCSTR:1984.5124-tr-84, California Institute of Technology, 1984.

A. J. Martin, Limitations to Delay-Insensitivity in Asynchronous Circuits Rapport technique CaltechCSTR:1990.cs-tr-90-02, California Institute of Technology, 1990.
DOI : 10.1007/978-1-4612-4476-9_35

URL : http://authors.library.caltech.edu/26721/2/postscript.pdf

A. J. Martin, Programming in VLSI: from communicating processes to delay-insensitive circuits (éditeur): Developments in concurrency and communication, The UT Year of Programming Series, pp.1-64, 1990.

A. J. Martin, Synthesis of Asynchronous VLSI Circuits Rapport technique CaltechCSTR:1991.cs-tr-93-28, California Institute of Technology, 1991.

F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip. INTEGRATION, the VLSI journal, pp.69-93, 2004.

[. Manohar and A. J. Martin, Quasi-Delay-Insensitive Circuits are Turing-Complete. Rapport technique CaltechCSTR:1995.cs-tr-95-11, California Institute of Technology, 1995.

A. J. Martin and M. Nyström, Asynchronous Techniques for Systemon-Chip Design, Proceedings of the IEEE, pp.1089-1120, 2006.

A. Ivan-miro-panades, S. Greiner, and . Abbas, Micro-réseau sur puce compatible avec l'approche GALS, JNRDM'06: Journées Nationales du Réseau Doctoral en Microélectronique, 2006.

A. Ivan-miro-panades, A. Greiner, and . Sheibanyrad, A Low Cost Network-on-Chip with Guaranteed Service Well Suited to the GALS Approach, NanoNet'06: proceedings of the first International Conference ON nANO-nETWORKS, pp.1-5, 2006.

C. J. Myers, ASYNCHRONOUS Circuit Design, 2001.
DOI : 10.1002/0471224146

[. Nyström and A. J. Martin, Crossing the Synchronous-Asynchronous Divide, Proceedings of the Workshop on Complexity- Effective Design. [OSC02] OSCI (Open SystemC Initiative): Functional Specification for SystemC 2.0, 2002.

[. Pilone and N. Pitman, UML 2.0 in a Nutshell, 2005.

J. Quartana, Design of Asynchronous Network on Chip: application to GALS systems, Thèse de doctorat, Institut National Polytechnique de Grenoble (INPG), 2004.
URL : https://hal.archives-ouvertes.fr/tel-00008830

]. M. Ren00 and . Renaudin, Asynchronous circuits and systems: a promising design alternative, Microelectronic Engineering, vol.54, issue.12, pp.133-149, 2000.

[. Renaudin, Etat de l'art sur la conception des circuits asynchrones: perspectives pour l'intégration des systèmes complexes, 2002.

L. Romain, Conception et modélisation d'un système de contrôle d'applications de télécommunication avec une architecture de réseau sur puce (NoC), Thèse de doctorat, Institut National Polytechnique de Grenoble (INPG), 2006.

[. Rotenberg, Conception et modélisation d'une architecture superscalaire et modulaire de traitement du signal fondée sur la logique asynchrone. Diplôme de recherche technologique, 2007.

[. Rose, S. Swan, J. Pierce, and J. Fernandez, Transaction Level Modeling in SystemC. rapport technique, Open SystemC Initiative, 2005.

[. Sutter and A. Alexandrescu, C++ Coding Standards: 101 Rules, Guidelines, and Best Practices. C++ in Depth Series, 2004.

E. Ivan, J. Sutherland, and . Ebergen, Computers without Clocks, Communications of the ACM, vol.32, issue.6, pp.720-738, 1989.

[. Sparsø and S. Furber, Principles of Asynchronous Circuit Design: A Systems Perspective, pp.153-218, 2001.
DOI : 10.1007/978-1-4757-3385-3

[. Sheibanyrad and A. Greiner, Two efficient synchronous asynchronous converters well-suited for networks-on-chip in GALS architectures, Integration, the VLSI Journal, vol.41, issue.1, pp.17-26, 2008.
DOI : 10.1016/j.vlsi.2007.04.006

URL : https://hal.archives-ouvertes.fr/hal-01199004

[. Sheibanyrad, I. M. Panades, and A. Greiner, Systematic Comparison between the Asynchronous and the Multi-Synchronous Implementations of a Network on Chip Architecture, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1090-1095, 2007.
DOI : 10.1109/DATE.2007.364439

URL : https://hal.archives-ouvertes.fr/hal-01311482

F. Viaud, A. Pêcheux, and . Greiner, An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles European Design and Automation Association, Proceedings of the conference on Design, automation and test in Europe, pp.94-99, 2006.

. G. Wm01-]-catherine, A. J. Wong, and . Martin, Data-Driven Process Decomposition For Circuit Synthesis, ICECS'01: Proceedings of the IEEE International Conference on Electronics, Circuits and Systems, pp.539-546, 2001.

. G. Wm03-]-catherine, A. J. Wong, and . Martin, High-Level Synthesis of Asynchronous Systems by Data-Driven Decomposition, DAC '03: Proceedings of the 40th conference on Design automation, pp.508-513, 2003.

Y. Keneth, D. L. Yun, and . Dill, Automatic synthesis of 3D asynchronous state machines, ICCAD'92: Proceedings of the International Conference on Computer-Aided Design, pp.576-580, 1992.

C. Koch-hofer and M. Renaudin, Timed Asynchronous Circuits Modeling and Validation using SystemC Dans Eugenio Villar (éditeur) : Embedded Systems Specification and Design Languages : Selected Contributions from FDL'07, pp.15-29

C. Koch-hofer and M. Renaudin, Timed Asynchronous Circuits Modeling and Validation Using SystemC, Proceedings of the 9th Forum on specification and Design Languages, 2007.
DOI : 10.1007/978-1-4020-8297-9_2

C. Koch-hofer, M. Renaudin, Y. Thonnart, and P. Vivet, ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC, First International Symposium on Networks-on-Chip (NOCS'07), 2007.
DOI : 10.1109/NOCS.2007.12

C. Koch-hofer and M. Renaudin, Modeling and synthesis of Asynchronous Network on Chip using SystemC, Special Workshop on Future Interconnects and Networks on Chip, 2006.