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Modélisation, Validation et Présynthèse de Circuits Asynchrones en SystemC

Abstract : With the technological advances in microelectronics, the traditional "fully synchronous" design methods of design are reaching their limits. An efficient solution to address this problem is to divide a circuit in several independent clock domains and to interconnect them with an asynchronous network on chip. However, the generalization of this solution is restricted by the lack of tools adapted to the design of complex asynchronous circuits like asynchronous network on chips. A contribution of this thesis, for lifting this restriction, has been to develop the ASC library to properly model delay insensitive asynchronous circuits in SystemC. Tracing facilities, based on a distributed timing model, were also developed to allow the validation by simulation of an ASC model. The last contribution of this thesis has been to define a presynthesis method for conditional statements which efficiently handles the synchronization mechanisms specific to asynchronous circuits.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, May 26, 2009 - 4:27:00 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Monday, October 15, 2012 - 11:10:10 AM


  • HAL Id : tel-00388418, version 1




C. Koch-Hofer. Modélisation, Validation et Présynthèse de Circuits Asynchrones en SystemC. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2009. Français. ⟨tel-00388418⟩



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