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Design and development of a recongurable cryptographic co-processor

Abstract : Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more exibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) [1] or Data Encryption Standard (DES) [2]. Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA) [3]. These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the exible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other security circuits.
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Contributor : Daniele Fronte <>
Submitted on : Thursday, February 26, 2009 - 9:15:25 PM
Last modification on : Thursday, March 15, 2018 - 4:56:06 PM
Long-term archiving on: : Tuesday, June 8, 2010 - 8:21:44 PM


  • HAL Id : tel-00364723, version 1



Daniele Fronte. Design and development of a recongurable cryptographic co-processor. Micro and nanotechnologies/Microelectronics. Université de Provence - Aix-Marseille I, 2008. English. ⟨tel-00364723⟩



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