Abstract : The aim of this dissertation was to develop protections structures against electrostatic discharges (ESD) dedicated to high voltages (40V100V) Inputs/Outputs, in the context of automotive or Ethernet applications. To fulfill this kind of specification, characterized by a narrow ESD design window, the protection should exhibit an electrical characteristic with a soft snapback, or no snapback, a high operating voltage and a low on-state resistance (RON). Beside, the required ESD robustness is at least 2kV HBM (Human Body Model), and could achieve 8 kV. We have chosen to realize these protections with self-biased bipolar transistors, which have attractive robustness and RON properties. In a first step, we have lead a thorough theoretical study in order to determine the parameters controlling the triggering and the on-state behavior under high current densities and high temperatures conditions. In particular, a new model was proposed to describe the injection ratio variations when its value is very low values. By taking advantage of this description, design guidelines were defined. In this work, we proposed have several solutions which satisfy the high voltage I/O requirements. Four types of innovative protections were developed: PNP bipolar transistors with an optimized RON, structures in which a lateral PNP transistor is coupled with a vertical diode, very low gain NPN transistors, and NPN transistors with a floating region in the base or the collector. In each case, the analysis of the physical mechanisms by 2D electrothermal simulation has lead to define appropriate optimization strategies. The best results have allowed reducing by two the surface, compared to the standard solution based on a stack of several low voltages protections.