D. Opérateur, 17 11 L'architecture de l'étage de l'opérateur, 18 12 L'emplacement de la quantication dans le papillon

R. Performances, 12) over GF (17) and RS(15,11) over GF (16) with BPSK modulation on AWGN channel. (F.E: Frequency Encoding)), p.86

E. Device and .. , 4 )) implementation results on STRATIX II, FFT-15 (over GF, p.142

W. Tuttlebee, Software Dened Radio: Enabling Technologies, 2002.

J. H. Reed, SoftWare Radio: A Modern Appoach to Radio Engineering, 2002.

R. H. Walden, Performance trends for analog to digital converters, IEEE Communications Magazine, vol.37, issue.2, pp.96-101, 1999.
DOI : 10.1109/35.747256

H. Tsurumi and Y. Suzuki, Broadband RF stage Architecture for Software-Dened Radio in Handheld Applications, IEEE Communications Magazine, 1999.

T. Hentschell, M. Henker, and G. Fettweis, The Software Front-End of Software Radio Terminals IEEE Personal Communications, 1999.

T. Hentschell, G. Fettweis, and M. Bronzel, Channelization and Sample Rate Adaptation in Software Radio Terminals, pp.121-126, 1998.

R. L. Lackey and D. W. , Speakeasy: the military software radio, IEEE Communications Magazine, vol.33, issue.5, 1995.
DOI : 10.1109/35.392998

P. G. Cook and W. Bonser, Architectural overview of the SPEAKeasy system, IEEE Journal on Selected Areas in Communications, vol.17, issue.4, 1999.
DOI : 10.1109/49.761042

B. Tarver, E. Christensen, and A. Miller, Digital modular radio (DMR) as a maritime/fixed Joint Tactical Radio System (JTRS), 2001 MILCOM Proceedings Communications for Network-Centric Operations: Creating the Information Force (Cat. No.01CH37277), 2001.
DOI : 10.1109/MILCOM.2001.985783

. Free-software-foundation, The GNU Software Radio

W. Tuttlebee, Software radio technology: a European perspective, IEEE Communications Magazine, vol.37, issue.2, 1999.
DOI : 10.1109/35.747260

D. Ikonomou, J. M. Pereira, and J. Da-silva, EU funded R-D on Re-congurable Radio Systems and Networks: The story so Far, 2000.

F. Jondral, A. Wiesler, and R. Machauer, A Software Dened Radio Structure for 2nd and 3rd Genaration Mobile Communications Standards, IEEE 6th Int. Symp. On Spread-Spectrum Tech. and Appli, 2000.

J. Palicot and C. Roland, FFT: a basic function for a reconfigurable receiver, 10th International Conference on Telecommunications, 2003. ICT 2003., 2003.
DOI : 10.1109/ICTEL.2003.1191527

C. Moy, J. Palicot, V. Rodriguez, and D. Giri, Optimal Determination of Common Operators for Multi-Standards Software-Dened Radio, IEEE WSR, 2006.

S. Kirpatrick, C. D. Gelatt, and M. P. Vecchi, Optimization by Simulated Annealing, Science, vol.220, issue.4598, pp.671-680, 1983.
DOI : 10.1126/science.220.4598.671

V. Rodriguez, C. Moy, and J. Palicot, Install or invoke?: The optimal trade-off between performance and cost in the design of multi-standard reconfigurable radios, Wireless Communications and Mobile Computing, vol.6, issue.9, pp.1-14, 2006.
DOI : 10.1002/wcm.487
URL : https://hal.archives-ouvertes.fr/hal-00182781

T. Magnanti and R. Wong, Network Design and Transportation Planning: Models and Algorithms, Transportation Science, vol.18, issue.1, pp.1-56, 1984.
DOI : 10.1287/trsc.18.1.1

J. Cavallaro and M. Vaya, VITURBO : A Recongurable Architecture for Viterbi and Turbo Coding, IEEE International Conference on Acoustics, speech, and Signal Processsing, 2003.

A. Wiesler and F. , A software radio for second- and third-generation mobile systems, IEEE Transactions on Vehicular Technology, vol.51, issue.4, 2002.
DOI : 10.1109/TVT.2002.1015347

M. Ghozzi, Intérêt des Techniques de Paramétrization pour des Archirtectures Radio Logicielle recongurables, 2004.

L. Alaus, D. Noguet, and J. Palicot, A Recongurable Linear Feedback Shift Register Operator for Software Dened Radio Terminal, ISWPC, 2008.

J. W. Cooley and J. W. Tukey, An algorithm for the machine calculation of complex Fourier series, Mathematics of Computation, vol.19, issue.90, pp.297-301, 1965.
DOI : 10.1090/S0025-5718-1965-0178586-1

E. R. Ferrara, C. F. Cowan, and P. M. Grant, Frequency Domain Adaptive Filtering, 1995.

D. Mansour and A. H. Gray, Unconstrained frequency-domain adaptive filter, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.30, issue.5, p.5, 1982.
DOI : 10.1109/TASSP.1982.1163949

T. A. Schirtzinger, X. Li, and W. K. Jenkins, A comparison of three algorithms for blind equalization based on the constant modulus error criterion, 1995 International Conference on Acoustics, Speech, and Signal Processing, 1995.
DOI : 10.1109/ICASSP.1995.480414

K. Beberidis and J. Palicot, A block Quasi-Newton Algorithm implemented in the frequency domain, 1995.

K. Beberidis and J. Palicot, A frequency domain decision feedback equalizer for multi path echo cancellation, p.95, 1995.

K. Beberidis, A. Marava, P. Karaivazoglou, and J. Palicot, Robust and Fast Converging Decision Feedback Equalizer Based on a New Adaptive Semi Blind Estimation Algorithm, 2001.

D. Chase, Class of algorithms for decoding block codes with channel measurement information, IEEE Transactions on Information Theory, vol.18, issue.1, pp.170-182, 1972.
DOI : 10.1109/TIT.1972.1054746

R. Pyndiah, A. Glavieux, A. Picart, and S. Jacq, Near optimum decoding of product codes, 1994 IEEE GLOBECOM. Communications: The Global Bridge, 1994.
DOI : 10.1109/GLOCOM.1994.513494

M. Davey and D. J. Mackay, Low-density parity check codes over GF(q), IEEE Communications Letters, vol.2, issue.6, pp.165-167, 1998.
DOI : 10.1109/4234.681360

D. Declercq and M. Fossorier, Decoding Algorithms for Nonbinary LDPC Codes over GF(q), IEEE. Trans. On Communications, vol.35, issue.4, 2007.

R. Blahut, Theory and Practice of Error Control Codes, 1983.

R. Blahut, Algebraic Codes for Data Transmission, 2003.
DOI : 10.1017/CBO9780511800467

J. M. Pollard, The fast Fourier transform in a nite eld, IEEE Trans. Comput, vol.25, pp.365-374, 1971.

W. C. Gore, Transmitting Binary Symbols with Reed-Solomon Codes, Proceedings of Princeton Conference on Information Sciences and Systems, pp.495-497, 1973.

A. Michelson, A Fast Transform in Some Galois Field and an application to Decoding Reed-Solomon Codes, IEEE International Symposium on Information Theory, p.49, 1976.

A. Lempel and S. Winograd, A new approach to error-correcting codes, IEEE Transactions on Information Theory, vol.23, issue.4, pp.503-508, 1977.
DOI : 10.1109/TIT.1977.1055735

R. T. Chien and D. M. Choy, Algebraic generalization of BCH-Goppa-Helgert codes, IEEE Transactions on Information Theory, vol.21, issue.1, pp.70-79, 1975.
DOI : 10.1109/TIT.1975.1055336

R. E. Blahut, Transform Decoding without Transform, presented at the Tenth IEEE Communication Theory Workshop, 1980.

S. M. Reddy and J. P. Robinson, Random error and burst correction by iterated codes, IEEE Transactions on Information Theory, vol.18, issue.1, pp.172-185, 1972.
DOI : 10.1109/TIT.1972.1054747

S. B. Wicker and V. K. Bhargava, Reed-Solomon codes and their applications, 1994.
DOI : 10.1109/9780470546345

C. Basile, The US HDTV standard, IEEE Spectrum, vol.32, issue.4, pp.36-45, 1995.
DOI : 10.1109/6.375998

W. W. Peterson, Encoding and error-correction procedures for the Bose-Chaudhuri codes, IEEE Transactions on Information Theory, vol.6, issue.4, pp.459-470, 1960.
DOI : 10.1109/TIT.1960.1057586

D. C. Gorenstein and N. Zierler, A Class of Error-Correcting Codes in $p^m $ Symbols, Journal of the Society for Industrial and Applied Mathematics, vol.9, issue.2, pp.207-214, 1961.
DOI : 10.1137/0109020

R. T. Chien, Cyclic decoding procedures for Bose- Chaudhuri-Hocquenghem codes, IEEE Transactions on Information Theory, vol.10, issue.4, pp.357-363, 1964.
DOI : 10.1109/TIT.1964.1053699

E. R. Berlekamp, Algebraic coding theory, 1986.
DOI : 10.1142/9407

J. L. Massey, Shift-register synthesis and BCH decoding, IEEE Transactions on Information Theory, vol.15, issue.1, pp.122-127, 1972.
DOI : 10.1109/TIT.1969.1054260

G. D. Forney, On decoding BCH codes, IEEE Transactions on Information Theory, vol.11, issue.4, pp.549-557, 1965.
DOI : 10.1109/TIT.1965.1053825

R. E. Blahut, Transform Decoding without Transform, presented at the Tenth IEEE Communication Theory Workshop, 1980.

R. E. Blahut, A Universal Reed-Solomon Decoder, IBM Journal of Research and Development, vol.28, issue.2, pp.150-158, 1984.
DOI : 10.1147/rd.282.0150

C. M. Rader, The number theoretic DFT and exact discrete convolution, Digital Signal Processing, 1972.

C. M. Rader, Discrete convolution via Mersenne transforms, IEEE Trans. Comput, issue.21, pp.1269-1273, 1972.

R. C. Agarwal and C. S. Burrus, Fast digital convolution using Fermat transforms, Southwest IEEE Conf. Rec, pp.538-543, 1973.

J. Justesen, On the complexity of decoding Reed-Solomon codes (Corresp.), IT-22, pp.237-238, 1976.
DOI : 10.1109/TIT.1976.1055516

S. W. Golomb, On the sum of the reciprocals of the Fermat numbers and related irrationalities, Canad, J. Math, vol.15, pp.475-478, 1963.

R. C. Agarwal and C. S. Burrus, Fast Convolution using fermat number transforms with applications to digital filtering, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.22, issue.2, 1974.
DOI : 10.1109/TASSP.1974.1162555

I. S. Reed, T. K. Truong, and L. R. Welch, The fast decoding of Reed-Solomon codes using Fermat transforms (Corresp.), IEEE Transactions on Information Theory, vol.24, issue.4, p.24, 1978.
DOI : 10.1109/TIT.1978.1055902

M. R. Best-;-h and . Roefs, Technical assistance channel coding investigation (spacecraft Telemetry, 1981.

M. Frigo and S. G. Johnson, FFTW: an adaptive software architecture for the FFT, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181), pp.1381-1384, 1998.
DOI : 10.1109/ICASSP.1998.681704

B. M. Baas and . Low-power, High-Performance 1024-point FFT Processor, IEEE Journal of Solid State Circuits, pp.380-387, 1999.

C. Y. Wang, C. B. Kuo, and J. Y. Jou, Hybrid Wordlength Optimization Methods of Pipelined FFT Processors, IEEE Transactions on Computers, vol.56, issue.8, pp.1105-1118, 2007.
DOI : 10.1109/TC.2007.1059

H. Sorensen, M. Heideman, and C. Burrus, On computing the split-radix FFT, IEEE Transactions on Acoustics, Speech, and Signal Processing, vol.34, issue.1, pp.152-156, 1986.
DOI : 10.1109/TASSP.1986.1164804

K. M. Elleithy and M. A. Bayoumi, Fast and flexible architectures for RNS arithmetic decoding, II: Analog and Digital Signal Processing, pp.191-201, 1977.
DOI : 10.1109/82.136572

R. Zimmermann, Binary Adder Architecture for Cell-Based VLSI and their Synthesis, 1998.

R. Zimmermann, Ecient VLSI Implementation of modulo (2 n ± 1) Addition and Multipication, Proc. 14th IEEE Symp. Computer Arithmetic, pp.158-167, 1999.

H. T. Vergos, C. Efstathiou, and D. Nikolos, Diminished-one modulo 2/sup n/+1 adder design, IEEE Transactions on Computers, vol.51, issue.12, pp.1389-1399, 2002.
DOI : 10.1109/TC.2002.1146705

C. Efstathiou, H. T. Vefos, D. Nikolos, and M. , Modulo 2/sup n/ ?? adder design using select-prefix blocks, IEEE Transactions on Computers, vol.52, issue.11, pp.1399-1406, 2003.
DOI : 10.1109/TC.2003.1244938

L. Kalamboukas, D. Nkolos, C. Efsthathiou, H. T. Vergosand, and J. Kalamatianos, High-speed parallel-prefix module 2/sup n/-1 adders, IEEE Transactions on Computers, vol.49, issue.7, pp.673-680, 2000.
DOI : 10.1109/12.863036

Z. Wang, G. A. Gulien, and W. C. Miller, An efficient tree architecture for modulo 2 n +1 multiplication, Journal of VLSI signal processing systems for signal, image and video technology, vol.45, issue.No. 3, pp.241-248, 1996.
DOI : 10.1007/BF00929618

J. Beuchat, Some modular adders and multipliers for field programmable gate arrays, Proceedings International Parallel and Distributed Processing Symposium, 2003.
DOI : 10.1109/IPDPS.2003.1213353

X. Lai and J. L. Massey, A Proposal for a New Block Encryption Standard, Advances in Cryptology-EUROCRYPT'90, pp.389-404, 1990.
DOI : 10.1007/3-540-46877-3_35

A. V. Curiger, H. Bonnenberg, and H. Kaeslin, Regular VLSI architectures for multiplication modulo (2/sup n/+1), IEEE Journal of Solid-State Circuits, vol.26, issue.7, pp.990-994, 1991.
DOI : 10.1109/4.92018

J. Beuchat, Modular multiplication for FPGA implementation of the IDEA block cipher, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003
DOI : 10.1109/ASAP.2003.1212864
URL : https://hal.archives-ouvertes.fr/inria-00072030

F. J. Taylor, Large moduli multipliers for signal processin, IEEE Trans. Circuits Syst, pp.731-736, 1981.

G. A. Julien, Implementation of Multiplication, Modulo a Prime Number, with Applications to Number Theoretic Transforms, IEEE Transactions on Computers, vol.29, issue.10, pp.899-905, 1980.
DOI : 10.1109/TC.1980.1675473

Y. Ma, A Simplied Architecture for Modulo (2 n + 1) Multiplication, IEEE Transactions on Computers, vol.47, issue.3, pp.333-337, 1998.

W. H. William, Yu and Shanzhen Xing Fixed-Point Multiplier Evaluation and Design with FPGA, Proceedings of SPIE, vol.3844, 1999.

B. Liu and T. , Thong, Fixed-Point Fast Fourier Transform Error Analysis, IEE Trans

A. Elterich and W. Stammler, Error analysis and resulting structural improvements for fixed point FFTs, ICASSP-88., International Conference on Acoustics, Speech, and Signal Processing, pp.1419-1422, 1988.
DOI : 10.1109/ICASSP.1988.196865

A. V. Oppenheim and C. J. Weinstein, Eects of Finite Register Length in Digital Filtering and The Fast Fourier Transform, Proc. IEEE, pp.957-976, 1972.

A. Jalali, Study and design of a digital Modem devoted to Multicarrier Modulation, University of Rennes 1, 1998.

Y. Wang and X. Zhu, A fast algorithm for the Fourier transform over finite fields and its VLSI implementation, IEEE Journal on Selected Areas in Communications, vol.6, issue.3, 1988.
DOI : 10.1109/49.1926

T. K. Truong, J. H. Jeng, and I. S. Reed, Fast algorithm for computing the roots of error locator polynomials up to degree 11 in Reed-Solomon decoders, IEEE Transactions on Communications, vol.49, issue.5, pp.779-783, 2001.
DOI : 10.1109/26.923801

S. V. Fedorenko and P. V. Trifonov, Finding roots of polynomials over finite fields, IEEE Transactions on Communications, vol.50, issue.11, pp.1709-1711, 2002.
DOI : 10.1109/TCOMM.2002.805269

S. V. Fedorenko and P. V. Trifonov, A method for Fast Computation of the Fast Fourier Transform over a Finite Field, Problems of Information Transmission, pp.231-238, 2003.

V. B. Afanasyev, On Complexity of FFT over Finite Field, Proc. 6th Joint Swedish-Russian Int.Workshop on Information Theory, pp.315-319, 1993.

T. K. Truong, P. D. Chen, L. J. Wang, I. S. Reed, and Y. Chang, Fast, prime factor, discrete Fourier transform algorithms over (2) for 8??????10, Information Sciences, vol.176, issue.1, pp.1-26, 2006.
DOI : 10.1016/j.ins.2004.10.001

. Elena, S. V. Costa, P. V. Fedorenko, and . Trifonov, On Computing the Syndrome Polynomial in Reed-Solomon Decoder, International ITG Conference on Sourcec and Channel Coding No, pp.337-342, 2004.

S. Gao, A New Algorithm for Decoding Reed-Solomon Codes, pp.55-68, 2003.
DOI : 10.1007/978-1-4757-3789-9_5

T. K. Truong, P. D. Chen, L. J. Wang, and T. C. Cheng, Fast transform for decoding both errors and erasures of Reed-Solomon codes over GF(2/sup m/) for 8/spl les/m/spl les/10, IEEE Transactions on Communications, vol.54, issue.2, pp.181-186, 2006.
DOI : 10.1109/TCOMM.2005.863804

C. S. Wallace, A Suggestion for a Fast Multiplier, IEEE Transactions on Electronic Computers, vol.13, issue.1, pp.14-17, 1964.
DOI : 10.1109/PGEC.1964.263830

]. L. Dadda, Some Shcemes for Parallel Multipliers, Alta Frequenza, vol.34, pp.349-356, 1965.

E. D. Mastrovito, Vlsi designs for multiplication over finite fields GF(2m), Proc. Sixth Int. Conf. Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes (AAECC-6), pp.297-309, 1988.
DOI : 10.1007/3-540-51083-4_67

C. S. Yeh, I. S. Reed, and T. K. Troung, Systolic Multipliers For Finite Fields GF(2m), IEEE Transactions on Computers, pp.33-357, 1984.

L. Gao and K. K. Parhi, Custom VLSI Design of Ecient Low Latency and Low Power Finite Field Multiplier for Reed-Solomon Codec, IEEE International Symposium on Circuits and Systems ISCAS'01, pp.574-577, 2001.

W. Drescher, G. Fettweis, and K. Bachmann, VLSI Architecture For Non-Sequential Inversion Over GF (2 m ) Using the Euclidean Algorithm, Int. Conf. On Signal Processing Applications and Technology, 1997.

J. Garcia and M. J. Schulte, A combined 16-bit binary and dual Galois field multiplier, IEEE Workshop on Signal Processing Systems, pp.63-68, 2002.
DOI : 10.1109/SIPS.2002.1049686