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Systeme a microprocesseur asynchrone basse consommation

Abstract : This Work presents a contribution to the design of asynchronous QDI (Quasi Delay insensitive) circuits for low power consumption. A quick study of the power estimation techniques will be shown. The methodology proposed will be presented in the chapter 2. This methodology uses 3 tools that perform the synthesis, optimization and the estimation of the asynchronous QDI circuits. The design of those circuits is done with a high level language for asynchronous circuits (CHP). The third chapter shows a study of different architectures to select the best one in terms of power consumption, speed and size. That chapter also shows a comparison between the equivalent synchronous circuits. In the final chapter, a technique for the reduction of the power consumption is presented. This technique changes the voltage of the circuit with a feedback control.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, December 23, 2008 - 10:22:01 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Tuesday, June 8, 2010 - 6:09:54 PM


  • HAL Id : tel-00349049, version 1




D. Rios. Systeme a microprocesseur asynchrone basse consommation. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2008. Français. ⟨tel-00349049⟩



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