R. Abelé, K. Fritschi, F. Boucart, P. Casset, A. M. Ancey et al., Suspended-Gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor A Novel Vertical Impact Ionisation MOSFET (I-MOS) Concept, IEEE International Electron Devices Meeting, pp.479-481, 2005.

I. Eisele, Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS), IEEE Electron Device Letters, vol.28, issue.1, pp.65-67, 2007.

M. Ionescu, R. T. Howe, H. P. Wong-aydin, A. Zaslavsky, S. Luryi et al., Lateral interband tunneling transistor in siliconon-insulatorMicrostructure and metal-insulating transition of vo 2 thin films Vertical Tunnel Field-Effect Transistor A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET Sub-50 nm high performance PDBFET with impact ionization, Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power LogicBéteille 99Bhuwalka 05] 70-nm Impact- Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs) " , IEEE International Electron Devices Meeting, pp.48-59, 1999.

F. Nemati and J. D. Plummer, Metal Insulator Transition A Novel Thyristor-based SRAM Cell (T- RAM) for High-speed, Low-Voltage, Giga-scale MemoriesNovel circuit aspects of the resonant gate transistor, European Solid State Device Research ConferenceNemati 99] IEEE International Electron Devices Meeting IEEE International Solid-State Circuits Conference, pp.287-290, 1966.

«. Schrott, E. Mott-field-effect-transistor, F. J. Seevinck, J. List, E. Lohstroh et al., Static Noise Margin Analysis of MOS SRAM CellsThe Kink- Related Excess Low-Frequency Noise in Silicon-on-Insulator MOST's, Applied Physics Letters IEEE Journal of Solid-State Circuits IEEE Transaction On Electron Devices, vol.73, issue.41, p.3, 1987.

J. Lander, F. Hooker, S. Cubaynes, M. Donnay, G. Jurczak et al., Planar Bulk MOSFETS Versus FinFETs: An Analog/RF Perspective Physics of Semiconductor Devices " , 2 nd EditionFundamentals of modern VLSI devices Transient Behavior of the Kink Effect in Partially-Depleted SO1 MOSFET's, IEEE Transactions On Electron Devices IEEE Electron Device Letters IEEE Electron Device Letters, vol.53, issue.8, pp.3071-3079, 1995.

. Kwong, Schottky-Barrier S/D MOSFETs With High-K Gate Dielectrics and Metal-Gate Electrode, IEEE Electron Device Letters, vol.25, issue.5, pp.268-271, 2004.

C. L. Références, C. R. Anderson, K. Crowell, A. M. Boucart, C. Ionescu et al., Distribution Functions and Ionization rates for Hot Electrons in Semiconductors Threshold Voltage in Tunnel FETs: physical Definition, Extraction, Scaling and Impact on IC design Fabrication and Analysis of CMOS Fully-Compatible High Conductance Impact Ionization MOS (I-MOS) Transistors " , 36th European Solid State Device Research Conference 70-nm Impact- Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs) Effect of Source Extension Junction Depth and Substrate Doping Concentration on I-MOS Device Characteristics Ionization Rates for Electrons and Holes in SiliconTemperature Dependence of Avalanche Multiplication in Semiconductors, Threshold Energies for Electron Hole Pair Production by Impact Ionization in Semiconductors 37th European Solid State Device Research Conference IEEE International Electron Devices MeetingFringing Fields in sub-0.1 m fully depleted SOI MOSFETs: optimization of the device architecture, pp.2267-2272, 1958.

M. Ershov, V. Ryzhii, N. O-3a, P. G. Gibbsons, and J. Kocsis, High Field Electron Transport in SiGe Alloy [Faktor 65] M.M. Faktor and J.I. Carasso, " Tetragonal Germanium Dioxide and Equilibria in the Ge-O-H System Breakdown Voltages of Germanium Plane- Cylindrical Junctions, Japanese Journal of Applied Physics Journal of Electrochemical Society IEEE Transactions on Electron Devices, vol.112, issue.12, pp.1365-1371, 1965.

]. B. Gonzaleza, V. Palankovskib, H. Kosinab, A. Hernandeza, and S. Selberherrb, An energy relaxation time model for device simulation, Solid-State Electronics, vol.43, issue.9, pp.1791-1795, 1999.
DOI : 10.1016/S0038-1101(99)00132-X

K. Gopalakrishnan, P. B. Griffin, J. Plummer-tang, H. Kosina, S. Selberherr et al., Electron and Hole Ionization Rates in Epitaxial Silicon at high Electric Fields A Review of Hydrodynamic and Energy-Transport Models for Semiconductor Device Simulation Reliability Characteristics of High-k Gate Dielectrics HfO2 in Metal Oxide Semiconductor capacitor Issue 1-4 Breakdown Voltage in Ultra Thin PiN Diodes Analysis of the Spurious Negative Resistance of PN Junction Avalanche Breakdown A New Recombinaison Model for Device Simulation Including Tunneling Analysis of Source/Drain structures on GeOI MOSFETs: Ge doping, Ge junctions and Metal/Ge contacts Theory of Tunneling Impact Ionization coefficients in Si1-xGex Carrier mobility in advanced CMOS devices with metal gate and HfO2 gate dielectric Mobility-Enhancement Technologies A physically based mobility model for numerical simulation of nonplanar devices, Impact Ionization MOS (I-MOS) ? Part I : Device and circuit Simulations IEEE Circuits & Devices Magazine IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.69-76, 1961.

]. V. Mazure, G. Carron, S. Rolland, J. M. Minoret, L. Hartmann et al., Nickel Selective Etching Studies for Self-Aligned Silicide Process in Ge and SiGe-Based Devices Wet Etching Step Evolution for Selective Removal on Silicide or Germanide Applications Preamorphization Implantation- Assisted Boron Activation in Bulk Germanium and Germanium-On-Insulator, GeOI) substrates -A Novel Engineered Substrate For Future High Performance Devices. Materials, pp.444-448, 1995.

S. Choi, J. Y. Song, J. D. Lee, Y. J. Park, B. J. Park et al., 70-nm Impact- Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs) Effect of Source Extension Junction Depth and Substrate Doping Concentration on I-MOS Device Characteristics Identification of the dominant diffusing species in silicide formation Germanium n-type Shallow Junction Activation DependencesReview of Some Critical Aspects of Ge and GeOI Substrates, High Current Drive in Ultra-Short Impact Ionization MOS (I-MOS) Devices IEEE International Electron Devices MeetingClavelier 07] L. Clavelier, F. Mayer, M. Vinet and S. Deleonibus, pp.1-4, 1974.

J. F. Damlencourt, B. Vincent, P. Rivallin, P. Holliger, D. Rouchon et al., Fabrication of SiGe- On-Insulator by Improved Ge condensation technique, International SiGe Technology and Device Meeting, pp.202-203, 2006.

F. Akatsu and . Letertre, 200 mm Germanium-On-Insulator (GeOI) Structures Realized from Epitaxial Wafers Using the Smart Cut TM Technology, pp.2005-2011, 2005.

S. Gaudet, C. Detavernier, A. J. Kellock, P. Desjardins, C. Lavoie et al., Thin film reaction of transition metals with germanium, IEEE International Electron Devices Meeting, pp.474-485, 2002.
DOI : 10.1116/1.2191861

J. Huang, N. Wu, Q. Zhang, C. Zhu, A. Tay et al., Germanium n+/p junction formation by laser thermal annealing process On the Extraction of Dopant Activation Level for Boron-doped Thin Germanium-On-Insulator (GeOI) Doping of Germanium by Phosphorus Implantation: Prediction of Diffused Profiles with Simulation, Resist Stripping Process on Germanium: A Basic Post-implant Study, 2005.

B. Renault, V. Guigues, S. Cosnier, and . Deleonibus, Germanium/HfO2/TiN Gate Stacks for Advanced Nodes: Influence of Surface Preparation on MOS Capacitor characteristics, 35th European Solid-State Device Research Conference (ESSDERC), pp.97-100, 2005.

C. , L. Royer, L. Clavelier, V. Mazzocchi, P. Rivallin et al., Optical and Electrical Characterization of Thin Germanium-On-Insulator (GeOI) Implanted Layers, SOI conference, pp.31-32, 2006.

L. Augendre, H. Sanchez, V. Grampeix, V. Mazzocchi, Y. Carron et al., Germanium-On-Insulator MOS Transistor Integration: Challenges and Opportunities for Advanced Technologies, Materials Science in Semiconductor Processing, 2008.

N. Jalaguier, C. Kernevez, . D. Mazure-]-e, C. S. Marshall, C. S. Wu et al., Simply irresistible silicides Metal-germanium contacts and germanide formation Experimental Investigation of the Impact of Implanted Phosphorus Dose and Anneal on Dopant Diffusion and Activation in Germanium Nickel Metallization Process for Low Resistance Contact Formation on Planar Co- Integration nMOS-Si and pMOS-Ge on Insulator Distinctly different thermal decomposition pathways of ultrathin oxide layer on Ge and Si surfaces Diffusion, Activation and Recrystallization of Boron Implanted in Preamorphized and Crystalline Germanium A Novel Fabrication Technique of Ultrathin and Relaxed SiGe Buffer Layers with High Ge Fraction for Sub-100nm Strained Silicon-On-Insulator MOSFETs, GeOI) structure realized by the Smart Cut TM technology Proceedings 809 B 4.4Toh 05] E. Toh, G.H. Wang, G.Q. Lo, N. Balasubramanian, C.H. Tung, F. Benistant, L. Chan, G. Samudra and Y.C. Yeo, " A Novel CMOS Compatible Sommaire du Chapitre 4, pp.153-188, 1985.

I. Caractéristique, S. Gs-)-des-i-mos-sur, and .. , 102 III.1.a Impact de la polarisation V DS sur l'électrostatique, p.102

.. Etude-des-différentes-variantes-Étudiées, 106 III.2.a Etudes des I-MOS sur substrats Si 1-x Ge x OI, p.106

R. L. Références, A. G. Batdorf, G. C. Chynoweth, P. W. Dacey, K. K. Foy et al., Uniform Silicon p-n Junctions I Broad area Breakdown A simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET Threshold Voltage in Tunnel FETs: physical definition, extraction, scaling and impact on IC design, Journal of Applied Physics IEEE Transactions on electron devices ESSDERC, vol.31, issue.7, pp.1541-1547, 1960.

S. Choi, J. Y. Song, J. D. Lee, Y. J. Park, B. G. Park et al., 100 nm n-/p- Channel I-MOS Using a Novel Self-Aligned Structure 70-nm Impact- Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs) A New Parameter Extraction Method for Ultra Thin Oxide SOI MOSFET's, High Current Drive in Ultra-Short Impact Ionization MOS (I-MOS) Devices Effect of Dislocations on Breakdown in Silicon p-n Junctions IEEE SOI Conference, pp.1-4, 1958.

K. Gopalakrishnan, P. B. Griffin, J. Plummer, R. Woo, C. Jungemanngopalakrishnan-05b-]-k et al., Impact Ionization MOS (I-MOS) -Part II: Experimental Results Novel Very High IE Structures Based on the Directed BBHE Mechanism for Ultralow-Power Flash Memories Impact Ionization MOS (I-MOS) ? Part I : Device and circuit Simulations Theory of Tunneling, IEEE Transactions on Electron Devices IEEE Electron Device Letters IEEE Transactions on Electron Devices Journal of Applied Physics, vol.5232, issue.52 1, pp.77-8469, 1961.

O. Marinov, M. J. Deen, J. A. Tejada-]-f, C. Mayer, G. Le-royer et al., Theory of microplasma fluctuations and noise in silicon diode in avalanche breakdown Co-integration of 2mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit, Experimental and TCAD Investigation of the two Components of the I-MOS (Impact Ionization MOSFET) Switching, pp.1852-1857, 2006.

B. Tabone, S. Previtali, F. Deleonibus, C. Mayer, D. Le-royer et al., Impact of SOI Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performance " , submitted IEDM « Avalanche Breakdown Due to 3-D Effects in the Impact-Ionization MOS (I- MOS) on SOI: Reliability Issues Theory of Microplasma Instability in Silicon High quality Germanium-On-Insulator wafers with excellent hole mobility, Romanjek 08] K. Romanjek, L. Hutin, C. Le Royer, A. Pouydebasque, M.-A. Jaud, C, pp.1373-1378, 1961.

S. Mazzocchi, R. Soliveres, L. Truche, P. Clavelier, X. Scheiblin et al., High performance 70nm Gate Length Germanium-On-Insulator pMOSFET With High-k/Metal Gate Microplasmas in Silicon Rigorous Theory and Simplified Model of the Band to Band Tunneling in Si On the performance Limit of Impact-Ionization Transistors, ESSDERC 2008 accepted. [Rose 57], pp.19-34, 1957.

]. S. Sze, E. Sze, G. H. Toh, L. Wang, G. Q. Chan et al., Physics of Semiconductor Devices Strain and Materials Engineering for the I-MOS Transistor with an Elevated Impact- Ionization Region Device Physics and Guiding Principles for the Design of Double Gate Tunneling Field Effect Transistor with Silicon Germanium Source Heterojunction A complementary I-MOS Technology Featuring SiGe Channel and I-Region for Enhancement of Impact Ionization, Breakdown Voltage, and Performance Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications A Double- Spacer I-MOS Transistor With Shallow Source Junction and Lightky Doped Drain for Reduced Operating Voltage and Enhanced Device Performance, Tunnel Field effect Transistor without Gate Drain Overlap, pp.2778-2785, 2007.

V. Out, V in ) dans un repère tourné à 45° : la SNM représente alors l'amplitude maximum de la courbe obtenue (voir Figure II-2) Ce paramètre est extrait en régime statique. Pour des signaux d'entrée/sortie dynamiques

I. Figure, Illustration graphique de la SNM : diagonale du plus grand carré formé par les courbes V in (V out ) et V out (V in ). La SNM est calculée comme l'amplitude maximum de la courbe V in (V out )-V out (V in )

S. La-première-différence-avec-une-logique, . Sp, and . Dd, CMOS provient des fortes tensions d'alimentation nécessaires au fonctionnement du I-MOS qui imposent une double tension d'alimentation V SP et V SN respectivement pour le p-IMOS et le n-IMOS (au lieu de 0 et V DD en logique CMOS) Comme source et drain ne sont pas symétriques dans le I-MOS, les polarisations V SN et V SP sont appliquées sur la source. Pour limiter la complexité de l'étude, nous fixerons V

C. Au, le I-MOS nécessite une tension minimum entre source et drain pour maintenir l'avalanche, c'est-à-dire pour rester à l

S. Ainsi, V. Une-partie-de, V. Sn-/-p-est-transférée-À-la-sortie, and . Out, Ainsi, l'inverseur I-MOS ne commute pas entre ±V DD , ce qui rend la mise en série d'inverseurs I-MOS délicate. L'inverseur I-MOS peut nous a ensuite permis d'étudier des circuits à base de I-MOS. Dans ce chapitre, nous avons étudié des circuits 100% I-MOS et nous avons pu tirer des conclusions quant au fonctionnement du I- MOS dans un environnement circuit. Nous avons mis en évidence que le I-MOS ne peut pas être utilisé pour des applications de type miroir de courant, car contrairement au MOSFET, il n'y a pas de régime de saturation où le courant serait indépendant de V SD . Nous avons ensuite étudié l'inverseur I-MOS

I. De, +. Nécessite-une-double-alimentation, and . Dd-pour-faire-fonctionner-les-i-mos-n-et-p, Malgré cela, nous avons montré que les tensions de sortie étaient compatibles avec un deuxième étage d'inverseur I-MOS. Finalement, l'inverseur I-MOS est plus proche dans son comportement d'un pont diviseur de tension Dans les états « 0 » et « 1 », l'inverseur ne consomme presque pas de courant et il s'avère plus stable que son équivalent CMOS. Cette amélioration de la stabilité est cohérente avec les études TCAD sur l'inverseur [Choi 05]. A cause des particularités du I-MOS listées ci-dessus, il est impossible d'utiliser un design de porte NAND ou NOR classique pour le I-MOS. C'est pourquoi nous avons proposé un design de porte NAND/NOR mieux adapté aux spécificités du I-MOS en combinant un inverseur et un miroir de courant. En terme de gain, nous avons mis en évidence une amélioration de 8% par rapport au design CMOS classique. Nous avons aussi vérifié que la porte NAND est plus stable que la porte MOSFET (SNMx2.4). L'inconvénient majeur de cette structure vient de la forte consommation statique engendrée pour certaines combinaisons d'entrée. Cela peut être résolu en diminuant le courant de contrôle I in à des valeurs inférieures au pico ampère, mais reste très restreignant, Les performances des circuits à base de I-MOS peuvent être améliorées en utilisant des alimentations dissymétriques ou en utilisant des travaux de sortie différents pour les grilles des transistors de type n et p. En ce qui concerne les tensions d'alimentation, elles peuvent être réduites en diminuant L IN ou en utilisant un matériau faible gap comme le Ge [Mayer 07b]. Bien que ces résultats aient été obtenus avec une technologie mature, les circuits 100% I- MOS ne seront pas plus compétitifs que les circuits CMOS avec une technologie plus agressive

I. En-technologie, avantage d'avoir une faible pente sous le seuil (S<60mV/dec) est contrebalancé par une tension de seuil variable avec V SD Une solution serait peut être de cointégrer des CMOS et des I-MOS au sein d'un même circuit, dans le quel le I-MOS « doperait » localement les performances tandis que le comportement global du circuit resterait proche de celui d'un circuit CMOS. Finalement, ce modèle a été mis à disposition des concepteurs

W. Y. Références, J. Y. Choi, J. D. Song, Y. J. Lee, B. J. Park et al., 70-nm Impact- Ionization Metal-Oxide-Semiconductor (I-MOS) Devices Integrated with Tunneling Field-Effect Transistors (TFETs) Generalized Scale Length for Two- Dimensional Effects in MOSFET's, IEEE Electron Device Letters, vol.19, pp.975-978, 1998.

A. J. Smit, D. B. Scholten, and . Klaasen, PSP : An Advanced Surface- Potential-Based MOSFET Model for Circuit Simulation, IEEE Transactions on Electron Devices, vol.53, pp.1979-1993, 2006.

K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, J. Plummer et al., Impact Ionization MOS (I-MOS) ? Part I: Device and circuit simulations A New Analytical Diode Model Including Tunnelling and Avalanche Breakdown An Explicit surface-potential-based MOSFET model for circuit simulation A 2D Analytical Solution for SCEs in DG MOSFETs, Hurkx 92], pp.69-76, 1992.

H. Yeo, F. Model-for-i-mos-device, C. Mayer, G. Le-royer, L. Le-carval et al., Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the CircuitAnalytical and Compact Modelling of the I-MOS (Impact Ionization MOS), Comparative Study of the fabricated and simulated Impact Ionization MOS (IMOS), pp.1852-1857, 2006.

F. Mayer, G. Billiot, T. Poiroux, C. L. Royer, S. Deleonibus et al., CI-MOS (Impact Ionization MOSFET) based Circuits: Inverters, Current Mirrors and Logic Gates [Mentor] Mentor Graphics Eldo User's Manual Safe design for TF-SOI power MOSFETs Static-Noise Margin Analysis of MOS SRAM Cells, Solid-State Electronics Electronics Letters IEEE Journal of Solid-State Circuits, vol.4222, issue.4, pp.748-754, 1987.

I. Yeo, C. Transistors, J. Q. Shen, E. H. Lin, K. F. Toh et al., On the performance Limit of Impact-Ionization Transistors Scaling Theory for Double Gate SOI MOSFET's Strain and Materials Engineering for the I-MOS Transistor with an Elevated Impact- Ionization Region, Physics of Semiconductor Devices " , 2 nd Edition Physics-Based Mathematical Conditioning of the MOSFET Surface Potential Equation Transactions on Electron Devices, pp.608-609, 1993.

S. Previtali, F. Deleonibus, T. Mayer, G. Poiroux, L. Le-carval et al., Analytical and Compact Modelling of the I-MOS (Impact Ionization MOS) Cointegration of 2mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS Comparative Study of the fabricated and simulated Impact Ionization MOS (IMOS) Deleonibus, « Avalanche Breakdown Due to 3-D Effects in the Impact-Ionization MOS (I-MOS) on SOI: Reliability IssuesExperimental and TCAD Investigation of the two Components of the I-MOS (Impact Ionization MOSFET) Switching Static and Dynamic TCAD Analysis of IMOS Performance: From the Single Device to the Circuit, Impact of SOI, Si 1-x Ge x OI and GeOI substrates on CMOS compatible Tunnel FET performanceCI-MOS (Impact Ionization MOSFET) based Circuits: Inverters, Current Mirrors and Logic Gates Solid-State Electronics Brevets : L. Clavelier, F. Mayer, M. Vinet and S. Deleonibus, pp.291-294, 2006.