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Etude, réalisation et caractérisation du transistor à ionisation par impact (I-MOS)

Abstract : The impact ionization transistor (I-MOS) is a new architecture enabling subthreshold slope smaller than 60mV/dec at room temperature, which is the intrinsic limit of the MOSFET architecture. The I-MOS is composed of a PiN diode, whose intrinsic area is partially covered by a gate. The target of this thesis is the performance evaluation of this new transistor from the single device to the circuit, as a potential post CMOS candidate. This device has been studied by the mean of TCAD simulations in order to investigate the I-MOS operation and to understand the underlying physics. Our I-MOS devices have been fabricated on SOI, Si1-xGexOI and GeOI substrates. Furthermore, we have proposed an innovative fabrication process for the I-MOS architecture. The fabricated I-MOS have been tested in order to verify the basic proprieties of the device and their performance has been compared to the co-integrated MOSFET. The band to band tunnelling operation mode as also been observed. We have developed an analytical model for the I-MOS, which shows good results. This model has been integrated in a SPICE simulator and I-MOS based circuit simulations have been carried out.
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Contributor : Frédéric Mayer <>
Submitted on : Monday, November 24, 2008 - 10:16:53 PM
Last modification on : Thursday, June 11, 2020 - 5:04:04 PM
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  • HAL Id : tel-00341292, version 1




Frédéric Mayer. Etude, réalisation et caractérisation du transistor à ionisation par impact (I-MOS). Physique [physics]. Université Joseph Fourier; Université Joseph-Fourier - Grenoble I, 2008. Français. ⟨tel-00341292⟩



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