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Fault tolerance through self-configuration in the future nanoscale multiprocessors

Piotr Zajac 1
1 LAAS-TSF - Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique
LAAS - Laboratoire d'analyse et d'architecture des systèmes
Abstract : This thesis is a contribution at the architectural level to the improvement of fault-tolerance in massively defective multi-core chips fabricated using nanometer transistors. The main idea of this work is that a chip should be organized in a replicated architecture and become as autonomous as possible to increase its resilience against both permanent defects and transient faults occurring at runtime. Therefore, we introduce a new chip self-configuration methodology, which allows detecting and isolating the defective cores, deactivating the isolated cores, configuring the communications and managing the allocation and execution of tasks. The efficiency of the methods is studied as a function of the fraction of defective cores, of defective interconnects and soft error rate.
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Submitted on : Friday, November 21, 2008 - 8:54:03 AM
Last modification on : Thursday, June 10, 2021 - 3:06:57 AM
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  • HAL Id : tel-00340508, version 1


Piotr Zajac. Fault tolerance through self-configuration in the future nanoscale multiprocessors. Réseaux et télécommunications [cs.NI]. INSA de Toulouse, 2008. Français. ⟨tel-00340508⟩



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