B. Godard, ]. J. Agin, H. Boyce, T. Trexler, and R. Rajsuman, Overcoming test challenges presented by embedded flash memory The VLSI Handbook Design and test of large embedded memories: An overview, IEMT 2003. IEEE/CPMT/SEMI 28th International Nonvolatile Semiconductor Memory Technology: A Comprehensive Guide to Understanding and Using NVSM Devices, pp.197-200, 1997.

H. Maes, Trends in semiconductor memoires Microelectronic Journal A 16K E/SUP 2/PROM employing new array architecture and designed-in reliability features Solid-State Circuits Integration of silicon nanocrystals into a 6V 4Mb non volatile memory array, Semiconductor Memories: Technology, Testing, and Reliability How far will silicon nanocrystals push the scaling limits of NVMs technologies, " IEDM Tech. Digest, pp.833-840, 1982.

E. Spitale, Effect of high-k materials in the control dielectric stack of nanocrystal memories, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850), p.161, 2004.
DOI : 10.1109/ESSDER.2004.1356514

M. Julliere, Tunneling between ferromagnetic films, Physics Letters A, vol.54, issue.3, pp.225-226, 1975.
DOI : 10.1016/0375-9601(75)90174-7

M. N. Baibich, Giant Magnetoresistance of (001)Fe/(001)Cr Magnetic Superlattices, Physical Review Letters, vol.61, issue.21, pp.2472-2475, 1988.
DOI : 10.1103/PhysRevLett.61.2472

S. S. Parkin, Exchange-biased magnetic tunnel junctions and application to nonvolatile magnetic random access memory (invited), Journal of Applied Physics, vol.85, issue.8, pp.5828-5833, 1999.
DOI : 10.1063/1.369932

N. Yamada, pseudobinary amorphous thin films for an optical disk memory, Journal of Applied Physics, vol.69, issue.5, pp.2849-2856, 1991.
DOI : 10.1063/1.348620

S. Lai and T. Lowrey, OUM - A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001.
DOI : 10.1109/IEDM.2001.979636

M. Gill, T. Lowrey, and J. Park, Ovonic unified memory -a highperformance nonvolatile memory technology for stand-alone memory and embedded applications Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. IEEE International, vol.1, pp.202-459, 2002.

V. Kynett, An in-system reprogrammable 32 K×8 CMOS flash memory Solid-State Circuits, IEEE Journal, vol.23, pp.1157-1163, 1988.

B. Van-zeghbroeck, Principles of Semiconductor Devices

K. Takeuchi, A source-line programming scheme for low voltage operation NAND flash memories, VLSI Circuits Digest of Technical Papers. 1999 Symposium on, pp.37-38, 1999.

D. C. Richard, The explosive word of serial flash, Electronic Component News, 2005.

S. Gregori, On-chip error correcting techniques for new-generation flash memories, Proceedings of the IEEE, vol.91, issue.4, pp.602-616, 2003.
DOI : 10.1109/JPROC.2003.811709

K. Park, A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond Digest of Technical Papers, VLSI Technology Symposium on, pp.19-20, 2006.

T. Ditewig, An embedded 1.2 V-read flash memory module in a 0, p.18

. Um-logic-process, Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. IEEE International, pp.34-35, 2001.

C. Peters, A 130nm high-density embedded EEPROM as universal memory for code and data storage on 1T FN/FN flash cell, Proceedings of the Non-Volatile Semiconductor Memory Workshop, pp.55-56, 2004.

S. Hamdioui, G. Gaydadjiev, and A. Van-de-goor, The state-of-art and future trends in testing embedded memories, Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004., pp.54-59, 2004.
DOI : 10.1109/MTDT.2004.1327984

H. Belgal, A new reliability model for post-cycling charge retention of flash memories, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), pp.7-20, 2002.
DOI : 10.1109/RELPHY.2002.996604

A. Birolini, Reliability Engineering: Theory and Practice, 2003.

O. Ginez, An Overview of Failure Mechanisms in Embedded Flash Memories, 24th IEEE VLSI Test Symposium, p.6, 2006.
DOI : 10.1109/VTS.2006.19

URL : https://hal.archives-ouvertes.fr/lirmm-00102761

P. Pavan, L. Larcher, and A. Marmiroli, Floating Gate Devices: Operation and Compact Modeling, 2004.

P. Pavan, Flash memory cells-an overview, Proceedings of the IEEE, pp.1248-1271, 1997.
DOI : 10.1109/5.622505

P. Kuhn, A reliability methodology for low temperature data retention in floating gate non-volatile memories, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167), pp.266-270, 2001.
DOI : 10.1109/RELPHY.2001.922912

J. B. Razafindramora, Modélisation et caractéristation de transistors MOS appliquées à l'étude de la programmation et du vieillissement de l'oxyde tunnel dans les mémoires EEPROM, 2004.

Y. Wern and S. Eric, Reliability characterization of a 0.6 /spl mu/m FLOTOX EPROM process, Semiconductor Electronics Proceedings. ICSE 2002. IEEE International Conference on, pp.490-499, 2002.

R. Degraeve, Analytical model for failure rate prediction due to anomalous charge loss of flash memories, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001.
DOI : 10.1109/IEDM.2001.979607

L. Larcher and P. Pavan, Statistical simulations to inspect and predict data retention and program disturbs in flash memories, IEEE International Electron Devices Meeting 2003, 2003.
DOI : 10.1109/IEDM.2003.1269201

R. Degraeve, Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224), 2001.
DOI : 10.1109/IEDM.2001.979447

F. Schuler, Physical description of anomalous charge loss in floating gate based NVM's and identification of its dominant parameter, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), pp.26-33, 2002.
DOI : 10.1109/RELPHY.2002.996606

R. Degreave, A new analytic model for the description of the intrinsic oxide breakdown statistics of ultra-thin oxides Reliability of Electron Devices, Failure Physics and Analysis, Proceedings of the 7th European Symposium on, pp.1639-1642, 1996.

R. Degraeve, Analytical Percolation Model for Predicting Anomalous Charge Loss in Flash Memories, Electron Devices, pp.1392-1400, 2004.
DOI : 10.1109/TED.2004.833583

B. and D. Salvo, Analysis of the electrical transport and reliability of floating gate non volatile memory insulators, 1999.

T. Ong, Erratic Erase In ETOX/sup TM/ Flash Memory Array Digest of Technical Papers, VLSI Technology Symposium on, pp.83-84, 1993.

A. Chimenton and P. Olivo, Erratic erase in flash memories. I. Basic experimental and statistical characterization, IEEE Transactions on Electron Devices, vol.50, issue.4, pp.1009-1014, 2003.
DOI : 10.1109/TED.2003.812098

A. Chimenton and P. Olivo, Erratic erase in flash memories. II. Dependence on operating conditions, IEEE Transactions on Electron Devices, vol.50, issue.4, pp.1015-1021, 2003.
DOI : 10.1109/TED.2003.812099

J. Portal, H. Aziza, and D. Nee, EEPROM memory: threshold voltage built in self diagnosis, International Test Conference, 2003. Proceedings. ITC 2003., pp.23-28, 2003.
DOI : 10.1109/TEST.2003.1270821

Y. Furuta and T. Okumura, United States Patent: 4218764 -Non-volatile memory refresh control circuit, 1980.

F. and L. Rosa, United States Patent: 6735733 -Method for the correction of a bit in a string of bits, 2004.

A. Hoefler, Statistical modeling of the program/erase cycling acceleration of low temperature data retention in floating gate nonvolatile memories, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320), pp.21-25, 2002.
DOI : 10.1109/RELPHY.2002.996605

J. Harthong, Probabilités & statistiques: De l'intuition aux applications, Diderot Arts et Sciences, 1980.

T. Tanzawa, A compact on-chip ECC for low cost flash memories Solid-State Circuits, IEEE Journal, vol.32, pp.662-669, 1997.

L. Joiner and J. Komo, Decoding binary BCH codes Southeastcon '95. 'Visualize the Future, Proceedings., IEEE, pp.67-73, 1995.

S. Morioka and Y. Katayama, Design methodology for a one-shot

M. Y. Hsiao, A Class of Optimal Minimum Odd-weight-column SEC-DED Codes, IBM Journal of Research and Development, vol.14, issue.4, p.395, 1970.
DOI : 10.1147/rd.144.0395

G. Cardarilli, Data integrity evaluations of Reed Solomon codes for storage systems [solid state mass memories] Defect and Fault Tolerance in VLSI Systems, Proceedings. 19th IEEE International Symposium on, pp.158-164, 2004.

E. Pardoux, Processus de markov et applications -algorithmes, réseaux, génome et finance : cours et exercices corrigés, Dunod, Traditional Reliability, vol.http, 1998.

C. Su, Y. Yeh, and C. Wu, An integrated ECC and redundancy repair scheme for memory reliability enhancement Defect and Fault Tolerance in VLSI Systems, DFT 2005. 20th IEEE International Symposium on, pp.81-89, 2005.

C. Hu and F. Hsu, United States Patent: 5511020 -Pseudo-nonvolatile memory incorporating data refresh operation, 1996.

C. Park, A low-cost memory architecture with NAND XIP for mobile embedded systems Hardware/Software Codesign and System Synthesis, pp.138-143, 2003.

L. Chang, On efficient wear leveling for large-scale flash-memory storage systems, Proceedings of the 2007 ACM symposium on Applied computing , SAC '07, pp.1126-1130, 2007.
DOI : 10.1145/1244002.1244248

J. Dumas, Théorie des codes : Compression, cryptage, correction, Dunod, 2006.

R. Hamming, Error detector and error correcting codes, The Bell System Technical Journal, 1950.

R. H. Morelos-zaragoza, The Art of Error Correcting Coding, 2002.

C. L. Chen and M. Y. Hsiao, Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review, IBM Journal of Research and Development, vol.28, issue.2, pp.124-134, 1984.
DOI : 10.1147/rd.282.0124

S. Gregori, An error control code scheme for multilevel Flash memories, Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, pp.45-49, 2001.
DOI : 10.1109/MTDT.2001.945227

S. Matarress and L. Fasoli, A method to calculate redundancy coverage for FLASH memories, Proceedings 2001 IEEE International Workshop on Memory Technology, Design and Testing, pp.41-44, 2001.
DOI : 10.1109/MTDT.2001.945226

N. Achouri, Techniques d'auto-réparation pour les mémoires à grandes densités de défauts, 2004.

T. Kawagoe, A built-in self-repair analyzer (CRESTA) for embedded DRAMs, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159), pp.567-574, 2000.
DOI : 10.1109/TEST.2000.894250

C. Huang, Built-in redundancy analysis for memory yield improvement, IEEE Transactions on, vol.52, pp.386-399, 2003.

Y. Hsiao, C. Chao-hsun-chen, and . Wu, A built-in self-repair scheme for NOR-type flash memory, Proceedings. 24th IEEE, p.6, 2006.

M. Choi, Optimal spare utilization in repairable and reliable memory cores, Proceedings the Third IEEE Workshop on Internet Applications. WIAPP 2003, pp.64-71, 2003.
DOI : 10.1109/MTDT.2003.1222363

V. Schober, S. Paul, and O. Picot, Memory built-in self-repair using redundant words, Proceedings International Test Conference 2001 (Cat. No.01CH37260), pp.995-1001, 2001.
DOI : 10.1109/TEST.2001.966724

X. Du, At-speed built-in self-repair analyzer for embedded word-oriented memories, Proceedings. 17th International Conference on, pp.895-900, 2004.

D. Bhavsar, An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.311-318, 1999.
DOI : 10.1109/TEST.1999.805645

M. Nicolaidis, N. Achouri, and L. Anghel, A diversified memory built-in selfrepair approach for nanotechnologies, Proceedings. 22nd IEEE, pp.313-318, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00005750

J. Li, A built-in self-repair scheme for semiconductor memories with 2-d redundancy, Proceedings. ITC 2003. International, pp.393-402, 2003.

S. Contributions, U. [. Patent, O. Godard, J. Ginez, and . Daga, Method and System for Providing a Nonvolatile Content Addressable Memory using a single FloTOx Element, p.11650104, 2007.

J. [. Godard and . Daga, Error Detecting/Correcting Scheme for Memories, p.12031289, 2008.

D. B. Godard, J. Daga, L. Torres, and G. Sassatelli, Architecture for Highly Reliable Embedded Flash Memories, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems
DOI : 10.1109/DDECS.2007.4295257

URL : https://hal.archives-ouvertes.fr/lirmm-00161636

J. [. Godard, L. Daga, G. Torres, and . Sassatelli, Evaluation of Design for Reliability Techniques in Embedded Flash Memories, 2007 Design, Automation & Test in Europe Conference & Exhibition, 2007.
DOI : 10.1109/DATE.2007.364529

URL : https://hal.archives-ouvertes.fr/lirmm-00179951

J. [. Godard, L. Daga, G. Torres, and . Sassatelli, Hierarchical Code Correction and Reliability Management in Embedded NOR Flash Memories " 13 th, IEEE European Test Symposium, 2008.

J. B. Godard, J. Daga, L. Torres, and G. Sassatelli, Évaluation de Techniques pour la Fiabilisation de Mémoires Flash Embarquées, Publications in national conferences proceedings (France) [ Journées Nationales du Réseau Doctoral de Microélectronique, pp.14-16, 2007.