Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles

Sébastien Le Beux 1
1 DART - Contributions of the Data parallelism to real time
LIFL - Laboratoire d'Informatique Fondamentale de Lille, Inria Lille - Nord Europe
Abstract : This PhD thesis presents a design flow for intensive signal processing applications, which are implemented on FPGA. This flow is based on Model Driven Engineering (MDE) and the specification of applications is done in UML.

The first contribution of this thesis is a metamodel, which identifies the concepts manipulated at the RTL level. These concepts are extracted from customized hardware implementations of massively parallel applications. The metamodel also take into account the FPGA characteristics and identify different abstraction levels of the FPGAs. These abstraction levels allow refining the hardware implementations.

The second contribution is a design flow, which transform applications modeled at high abstraction level model (in UML) into RTL models. According to the FPGA resources allocated, a process optimizes the hardware implementation thanks to loop transformations.

From a UML model, a VHDL code is automatically generated. The code is simulable and synthetizable on FPGA. The design flow has been successfully used in safety transport for the development of an anti-collision radar system.
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https://tel.archives-ouvertes.fr/tel-00322195
Contributor : Sébastien Le Beux <>
Submitted on : Thursday, September 18, 2008 - 7:10:37 PM
Last modification on : Thursday, February 21, 2019 - 10:52:48 AM
Long-term archiving on : Tuesday, September 21, 2010 - 5:47:27 PM

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Sébastien Le Beux. Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d'Ingénierie Dirigée par les Modèles. Autre [cs.OH]. Université des Sciences et Technologie de Lille - Lille I, 2007. Français. ⟨tel-00322195v2⟩

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