Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction Level

Abstract : The work presented in this document deals with the formal
verification models of Systems-on-a-Chip at the transaction level
(TLM). We present the transaction level and its variants, and remind
how this new level of abstraction is today necessary in addition to
the register transfer level (RTL) to accommodate the growing
constraints of productivity and quality, and how it integrates in
the design flow.

We present a new tool, called \lussy, that allows property-checking
on transactional models written in SystemC. Its structure is similar
to the one of a compiler: A front-end, Pinapa, that reads the
source program, a semantic extractor, bise, into our intermediate
formalism HPIOM, a number of optimizations in the component \birth,
and code generators for provers like Lustre and SMV.
Lussy has been designed to have as few limitation as possible
regarding the way the input program is written. \pinapa uses a novel
approach to extract the information from the SystemC program, and
the semantic extraction implements several TLM constructs that have
not been implemented in any other SystemC verification tool as of
now. It doesn't require any manual annotation. The tool chain is
completely automated.

Lussy is currently able to prove properties on small platforms. Its
components are reusable to build compositional verification tools,
or static code analyzers using techniques other than model-checking
that can scale up more efficiently.
We present the theoretical principles for each step of the
transformation, as well as our implementation. The results are given
for small examples, and for a medium size case-study called EASY.
Experimenting with Lussy allowed us to compare the various tools we
used as provers, and to evaluate the effects of the optimizations we
implemented.
Complete list of metadatas

https://tel.archives-ouvertes.fr/tel-00311033
Contributor : Matthieu Moy <>
Submitted on : Tuesday, August 12, 2008 - 2:30:08 PM
Last modification on : Monday, November 12, 2018 - 4:24:03 PM
Long-term archiving on: Friday, October 5, 2012 - 11:42:58 AM

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  • HAL Id : tel-00311033, version 1

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Matthieu Moy. Techniques and Tools for the Verification of Systems-on-a-Chip at the Transaction Level. Computer Science [cs]. Institut National Polytechnique de Grenoble - INPG, 2005. English. ⟨tel-00311033⟩

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