Etude, Modélisation et Amélioration des Performances des
Convertisseurs Analogique Numérique Entrelacés dans le Temps

Abstract : To comply with new telecommunication standard requirements, Analog to Digital ConverterADC should provide high sample rate, high resolution and low power consumption. With today's technologies, only one converter cannot achieve these requirements. To cope with this problem, one solution consists in parallelizing existing ADC cores on a die to increase the sampling rate for the same resolution and power consumption. The resulting system is called Time Interleaved Analog to Digital Converter TIADC. However, TIADC systems introduce new set of problem : indeed, each converter is characterized by its proper errors, mismatches between ADC cause undesirable spurs. The main thesis contribution is about TIADC spectral parameter loss study caused by mismatches effect, TIADC modelling and material description. A special attention is given to TIADC compensation methods by proposing two solutions : the first one is an offline method used for measurement applications. The second is an online method based on adaptive filtering for telecommunications applications. The first method is verified by experimental data, the second one is implemented into FPGA and verified by tests and measures.
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Submitted on : Thursday, July 17, 2008 - 8:54:14 AM
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  • HAL Id : tel-00298981, version 1

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Maher Jridi. Etude, Modélisation et Amélioration des Performances des
Convertisseurs Analogique Numérique Entrelacés dans le Temps. Micro et nanotechnologies/Microélectronique. Université Sciences et Technologies - Bordeaux I, 2007. Français. ⟨tel-00298981⟩

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