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Développement sur substrat SOI mince de composants N-MEMS de type capteur inertiel et étude de la co-intégration avec une filière CMOS industrielle

Abstract : This PhD aims to realize an inertial sensor on thin SOI substrates (160-nm thick for top Si), the same substrate used in the 130-nm CMOS technology node. The long term objective is to manufacture the sensor along with the IC using a horizontal co-integration process in order to address the requirements for public applications. This subject raises the question of the realization of a mechanical structure at the nanoscale. To realize an accelerometer demonstrator, we must answer many questions related to the manufacturing aspects and to the physical phenomena appearing at this scale. We first give an overview based on the state of the art on both NEMS and MEMS. This literature review allows us to foresee future questions raised by the complexity of the size reduction. We choose a demonstrator, a resonant accelerometer, which will be used as a study case for this work. We theoretically and experimentally study more deeply the nano metric basic structures behaviour. One of the main difficulties dealing with NEMS is to characterize the device in itself. Different considerations allow us to choose the capacitive detection and to show its theoretical feasibility. We realize in parallel the conception of the electromechanical part of the sensor and the definition of the IC sensor co-integration process flow, allowing us to get a direct electrical measurement. This work leads us to discuss the feasibility of nano-accelerometer for public applications. Thanks to the analysis of the results, we can present some perspectives related to the knowledge acquired through our study. We give some directions to be pursued for a better understanding of the conception, the manufacturing and the device characterization. We conclude on our choice for a demonstrator, and its ability to address different nano metric applications. The choice of SOI substrate (based on the 130-nm CMOS technology node) to manufacture NEMS is discussed along with the challenge to reduce the dimension and to combine together the IC and the NEMS performances.
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Contributor : Lucie Torella <>
Submitted on : Tuesday, July 1, 2008 - 11:44:56 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
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  • HAL Id : tel-00292361, version 1




T. Baron. Développement sur substrat SOI mince de composants N-MEMS de type capteur inertiel et étude de la co-intégration avec une filière CMOS industrielle. Micro et nanotechnologies/Microélectronique. Université Joseph-Fourier - Grenoble I, 2008. Français. ⟨tel-00292361⟩



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