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Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés

Alin Razafindraibe 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In the area of secure circuits design and more particularly of (Differential Power Analysis) DPAresistant ones, dual-rail logic looks like an interesting alternative to static CMOS logic. Indeed, the encoding style associated with this logic offers the opportunity to make power consumption balanced thus making DPA attacks impossible. In this context, we focused ourselves on the analysis of the assets and weaknesses of dual-rail logic and especially to its improvement. Firstly we showed that a dual-rail circuit is distinctly more resistant to DPA attacks than its counterpart single-rail. Secondly, after a thorough study of the physical synthesis impact on the robustness of dual-rail circuits, we arrived at the conclusion that in the presence of loads, input transition times and arrival times imbalances, dual-rail circuits can lose their advantage and become vulnerable to DPA attacks. This study made it also possible to define some metric robustness with respect to DPA attacks, from which we clearly established that a dual-rail cell is DPA-resistant if and only if every signals controlling it arrive in a particularly reduced interval time. In order to eliminate this residual weakness from dual-rail logic, we finally proposed a simple but effective improvement. The resulting logic was called STTL (Secured Triple Track Logic). At last, the implementation of this logic made it possible to show that STTL logic enables us to obtain circuits with running times and power consumption which are data independent.
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https://tel.archives-ouvertes.fr/tel-00282762
Contributor : Isabelle Gouat <>
Submitted on : Wednesday, May 28, 2008 - 12:01:33 PM
Last modification on : Friday, October 23, 2020 - 4:54:55 PM
Long-term archiving on: : Friday, May 28, 2010 - 8:27:57 PM

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  • HAL Id : tel-00282762, version 1

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Alin Razafindraibe. Analyse et amélioration de la logique double rail pour la conception de circuits sécurisés. Micro et nanotechnologies/Microélectronique. Université Montpellier II - Sciences et Techniques du Languedoc, 2006. Français. ⟨tel-00282762⟩

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