M. Abramovici, Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis, IEEE Transactions on Computers, vol.29, issue.6, pp.451-460, 1980.
DOI : 10.1109/TC.1980.1675604

]. M. Abr83, P. R. Abramovici, D. T. Menon, and . Miller, Critical Path Tracing -an Alternative to Fault Simulation, Proceedings of the 20th conference on Design automation, pp.214-220, 1983.

]. M. Amy06 and . Amyeen, Improving Precision Using Mixed-level Fault Diagnosis, Proceedings IEEE Int.Test Conf, pp.1-10, 2006.

]. Z. Bar83, B. K. Barzilai, and . Rosen, Comparison of AC Self-Testing Procedures, Proceedings of the International Test Conference, pp.89-94, 1983.

]. J. Car87, V. S. Carter, B. K. Iyengar, and . Rosen, Efficient Test Coverage Determination for Delay Faults, Proceedings of the International Test Conference, pp.418-427, 1987.

]. Y. Che06, J. J. Chen, and . Liou, Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method, Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp.428-438, 2006.

]. P. Eng03, I. Engelke, . Polian, . Renovell, and . Becker, Simulating Resistive Bridging and Stuck-At Faults, Proceedings of the International Test Conference, pp.1051-1059, 2003.

]. J. Gho00, N. A. Ghosh-dastidar, and . Touba, Diagnosing Resistive Bridges Using Adaptive Techniques, Proceedings of the IEEE Custom Integrated Circuits Conference, pp.79-82, 2000.

]. P. Gir92a, C. Girard, S. Landrault, and . Pravossoudovitch, Delay-Fault Diagnosis Based on Critical Path Tracing from Symbolic SimulationDelay-Fault Diagnosis by Critical-Path Tracing, Proceedings of the IEEE International Symposium on Circuits and Systems Proceedings of the IEEE Design & Test of Computers, pp.1133-1136, 1992.

H. Shi-yu, A Symbolic Inject-and-Evaluate Paradigm for Byzantine Fault Diagnosis, Journal of Electronic Testing: Theory and Applications, vol.19, issue.2, pp.161-172, 2003.

]. S. Hol07, H. Holst, and . Wunderlich, Adaptive Debug and Diagnosis without Fault Dictionaries, Proceedings of the 12 th IEEE European Test Symposium, pp.7-12, 2007.

]. E. Hsi77, R. Hsieh, L. Rasmussen, W. Vidunas, and . Davis, Delay Test Generation, Proceedings of the Design Automation Conference, pp.486-492, 1977.

]. K. Kis86, F. Kishida, Y. Shirotori, S. Ikemoto, T. Ishiyama et al., A Delay Test System for High Speed Logic LSI's, Proceedings of the Design Automation Conference, pp.786-790, 1986.

]. D. Lav98 and . Lavo, Diagnosing Realistic Bridging Faults with Single Stuck-At Information, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol.17, issue.3, pp.255-2671998

]. Y. Lev86, P. R. Levendel, and . Menon, Transition Faults in Combinational Circuit: Input Transition Test Generation and Fault Simulation, Proceedings of the Fault- Tolerant Computing Symposium, pp.278-283, 1986.

[. Lin, F. Lu, and K. Cheng, Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.5, pp.932-942, 2007.
DOI : 10.1109/TCAD.2006.884486

]. J. Liu05, A. Liu, and . Veneris, Incremental Fault Diagnosis, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems, vol.24, pp.2-240, 2005.

]. Lo00, P. C. Lo, . S. Chan, and . Menon, An Efficient Structural Approach to Board Interconnect Diagnosis Testable Design of BiCMOS Circuits for Stuck-Open Fault Detection using Single Patterns, Proceedings of the VLSI Test Symposium, pp.1239-1255, 1993.

]. I. Pom97 and . Pomeraz, On Dictionnary-Based Fault Location in Digital Logic Circuits, IEEE Transaction on Computers, vol.46, issue.1, pp.48-59, 1997.

]. A. Pra88, S. M. Pramanick, and . Reddy, On the Detection of Delay Faults, Proceedings of the International Test Conference, pp.845-856, 1988.

]. M. Sch87, F. Schulz, and . Brglez, Accelerated Transition Fault Simulation, Proceedings of the Design Automation Conference, pp.237-243, 1987.

]. G. Smi85 and . Smith, Model for Delay Faults Based upon Paths, Proceedings of the International test Conference, pp.342-349, 1985.

]. S. Ven97, W. K. Venkataraman, and . Fuchs, A Deductive Technique for Diagnosis of Bridging Faults, Proceedings of the Proceedings of the IEEE/ACM international conference on Computer-aided design, pp.562-567, 1997.

]. S. Ven01, S. B. Venkataraman, and . Drummonds, Poirot: applications of a logic fault diagnosis tool, IEEE Design & Test of Computer, vol.18, issue.1, pp.19-30, 2001.

]. J. Wai86, E. Waicukausky, B. Lindbloom, V. Rosen, and . Iyendar, Transition Fault Simulation by Parallel Pattern Single Fault Propagation, Proceedings of the International Test Conference, pp.542-549, 1986.

]. B. Wood87 and . Woodhall, Empirical Results on Undetected CMOS Stuck-Open Failures, Proceedings of the International Test Conference, pp.166-170, 1987.

A. Bibliographie-personnelle-conférences-avec-actes-et-comité-de-lecture, A. Rousset, P. Bosio, C. Girard, S. Landrault et al., Improving Diagnosis Resolution without Physical Information, IEEE International Symposium on Electronic Design, 2008.

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, Unified Framework for Logic Diagnosis, Proceedings of IEEE East-West Design & Test Workshop, pp.47-52, 2006.
URL : https://hal.archives-ouvertes.fr/lirmm-00096211

A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch et al., A Mixed Approach for Unified Logic Diagnosis, 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, pp.239-242, 2007.
DOI : 10.1109/DDECS.2007.4295289

URL : https://hal.archives-ouvertes.fr/lirmm-00161643

A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch et al., DERRIC: A Tool for Unified Logic Diagnosis, 12th IEEE European Test Symposium (ETS'07), pp.13-20, 2007.
DOI : 10.1109/ETS.2007.16

URL : https://hal.archives-ouvertes.fr/lirmm-00155993

A. Rousset, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch et al., Fast Bridging Fault Diagnosis using Logic Information, 16th Asian Test Symposium (ATS 2007), pp.33-38, 2007.
DOI : 10.1109/ATS.2007.75

URL : https://hal.archives-ouvertes.fr/lirmm-00179259

A. Colloques-sans-actes-ou-avec-actes-À-diffusion-restreinte, P. Rousset, S. Girard, C. Pravossoudovitch, A. Landrault et al., Unified Diagnostic Method Targeting Several Fault Models " ; VLSI PhD forum, 2007.

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, State-of-the-art Diagnosis of Delay Faults in Scan Environment, South European Test Seminar, 2005.

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, Unified Diagnostic Method Focusing Several Fault Models, 2006.

A. Rousset, A. Bosio, P. Girard, S. Pravossoudovitch, C. Landrault et al., A Comprehensive Diagnosis Methodology for Several Fault Models, 2007.

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, Méthode de diagnostic unifiée ciblant plusieurs modèles de fautes, 2006.

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, Diagnostic unifié ciblant plusieurs modèles de fautes, Journées Nationales du Réseau Doctoral de Microélectronique (JNRDM) 2006

A. Rousset, P. Girard, S. Pravossoudovitch, C. Landrault, and A. Virazel, Méthode de diagnostic unifiée pour circuits intégrés numériques, 2007.