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Analyse de sûreté par injection de fautes dans un environnement de prototypage à base de FPGA

Abstract : Technology downscaling increases the sensitivity of integrated circuits faced to perturbations (particles strikes, lose of signal integrity...). The erroneous behaviour of a circuit can be unacceptable and a dependability analysis at a high abstraction level enables to select the most efficient protections and to limit timing overhead induced by a possible rework. This PhD aims at developing a methodology and an environment which improves the dependability analysis of digital integrated circuits. The proposed approach uses a hardware prototype of an instrumented version of the design to be analyzed. The environment includes three levels of execution including an embedded software level that enables to speed-up the experiments while keeping an important flexibility: the user can obtain the best trade-off between the complexity of the analysis and the duration of the experiments. We also propose new techniques for the instrumentation and for the injection control in order to improve the performances of the environment. A predictive evaluation of the performances informs the designer on the most influent parameters and on the analysis duration for a given design and a given implementation of the environment. Finally the methodology is applied on the analysis of two significant systems including a hardware/software system built around a SparcV8 processor.
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Submitted on : Monday, April 21, 2008 - 11:11:53 AM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
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  • HAL Id : tel-00274706, version 1




Pierre Vanhauwaert. Analyse de sûreté par injection de fautes dans un environnement de prototypage à base de FPGA. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2008. Français. ⟨tel-00274706⟩



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