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Statistical analysis of the impact of within die variations on eSRAM internal signal races

Michael Yap San Min 1
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Aggressive technology scaling has led to the progressive de gradation of transistor performances due to variability conditions such as process, voltage and temperature fluctuations. To handle the impact of manufacturing processvariations along with the operating conditions in circuit design, corner based methodology is performed by characterizing the circuit under best case and worst case conditions(corner analysis method). However, the increase of variability in manufacturing processes results in an over estimation of performances, for instance like the read timing margin of an embedded SRAM. Hence, the only alternative to overcome the hurdle linked to corner analysis method is in the use of statistical design techniques, more specifically through statistical timing analysis. The statistical timing analysis of SRAM performances constitutes the essence of this thesis. First of all, we have shown the serious limitations associated with the corner analysis method as far as the read timing of the SRAM is concerned. Based on these results, we have then proposed a modelling approach as an alternative to the corner based method. This approach has then been used in the statistical sizing of the memory so as to optimize its timing performances, there by mitigating the excessive read timing margin introduced by the traditional method.
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Submitted on : Thursday, February 7, 2008 - 4:33:26 PM
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Michael Yap San Min. Statistical analysis of the impact of within die variations on eSRAM internal signal races. Micro and nanotechnologies/Microelectronics. Université Montpellier II - Sciences et Techniques du Languedoc, 2008. English. ⟨tel-00246549⟩

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