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Étude et modélisation compacte d'un transistor MOS SOI double-grille dédié à la conception

Abstract : We propose a compact model for symmetric MOS silicon on insulator (SOI) double-gate transistor. Our approach relies on the EKV formalism and offers the following characteristics: simple analytical solutions which describe dynamic and static behaviours, direct links between charges-voltages and voltages-current, a robust and accurate numerical inversion algorithm which allows for a great reduction in the computation time, easy implementation in the VHDL-AMS language demonstrating that the model insures fast and accurate simulations of the electrical characteristics.
The model takes into account the small geometry effects such as: the drain-induced barrier lowering, the charge sharing effects, subthreshold slope degradation and the carrier mobility degradation. Besides these effects, we have modeled the extrinsic capacitances.
The model is valid for devices with a channel length of 60nm. The validity is verified by comparing the results of the model with those of the numerical simulations performed with the Atlas device simulator from Silvaco.
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Contributor : Birahim Diagne <>
Submitted on : Wednesday, January 16, 2008 - 4:00:46 PM
Last modification on : Thursday, April 23, 2020 - 2:26:29 PM
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  • HAL Id : tel-00206167, version 1



Birahim Diagne. Étude et modélisation compacte d'un transistor MOS SOI double-grille dédié à la conception. Micro et nanotechnologies/Microélectronique. Université Louis Pasteur - Strasbourg I, 2007. Français. ⟨tel-00206167⟩



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