A. Bardsley and D. Edwards, Compiling the language Balsa to delay insensitive hardware
DOI : 10.1007/978-0-387-35064-6_11

A. Bardsley and D. Edwards, The balsa asynchronous circuit synthesis system, Forum on Design Languages, 2000.

P. A. Beerel, T. H. , and -. Meng, Automatic gate-level synthesis of speed-independent circuits, IEEE/ACM International Conference on Computer-Aided Design, pp.581-586, 1992.
DOI : 10.1109/ICCAD.1992.279309

P. A. Beerel, K. Y. Yun, and W. C. Chou, Optimizing average-case delay in technology mapping of burst-mode circuits, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp.244-259, 1996.
DOI : 10.1109/ASYNC.1996.494455

E. Beigné and P. Vivet, Design of On-chip and Off-chip Interfaces for a GALS NoC Architecture, 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06), pp.172-181, 2006.
DOI : 10.1109/ASYNC.2006.16

L. Benini, G. De, and . Micheli, A survey of Boolean matching techniques for library binding, ACM Transactions on Design Automation of Electronic Systems, vol.2, issue.3, pp.193-226, 1997.
DOI : 10.1145/264995.264996

K. Van and B. , Beware the isochronic fork. Integration, the VLSI journal, pp.103-128, 1992.

K. V. Berkel, Handshake Circuits : an asynchronous architecture for VLSI Programming, volume 5 of International Series on Parallel Computation, 1993.

K. V. Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken et al., A fully asynchronous low-power error corrector for the DCC player, IEEE Journal of Solid-State Circuits, vol.29, issue.12, pp.1429-1439, 1994.
DOI : 10.1109/4.340416

K. V. Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken et al., A single-rail re-implementation of a DCC error detector using a generic standard-cell library, Proceedings Second Working Conference on Asynchronous Design Methodologies
DOI : 10.1109/WCADM.1995.514644

K. V. Berkel, M. B. Josephs, and S. M. Nowick, Scanning the technology : Applications of asynchronous circuits, Proc. IEEE, pp.223-233, 1999.

E. Biham and A. Shamir, Differential cryptanalysis of the full 16-round DES, Advances in Cryptology CRYPTO'91 Proceedings, pp.487-496, 1992.

E. Biham and A. Shamir, Power analysis of the key scheduling of the AES candidates, Second AES Candidate Conference (AES2), 1999.

D. Borrione, M. Boubekeur, E. Dumitrescu, M. Renaudin, J. B. Rigaud et al., An approach to the introduction of formal validation in an asynchronous circuit design flow, 36th Annual Hawaii International Conference on System Sciences, 2003. Proceedings of the, 2003.
DOI : 10.1109/HICSS.2003.1174811
URL : https://hal.archives-ouvertes.fr/hal-00009578

F. Bouesse, Contribution à la conception de circuits intégrés sécurisés : l'alternative asynchrone, 2005.

F. Bouesse, M. Renaudin, B. Robisson, E. Beigné, P. Liardet et al., DPA on quasi delay insensitive asynchronous circuits : concrete results, XIX Conference on Design of Circuits and Integrated Systems (DCIS04), 2004.
URL : https://hal.archives-ouvertes.fr/hal-01399172

F. Bouesse, G. Sicard, and M. Renaudin, Efficient quasi delay insensitive asynchronous architectures for low EMI, EMC_Compo, 2005.

J. G. Bredeson, Synthesis of multiple input-change hazard-free combinational switching circuits without feedback???, International Journal of Electronics, vol.4, issue.6, pp.615-624, 1975.
DOI : 10.1080/00207217508920527

J. G. Bredeson and P. T. Hulina, Elimination of static and dynamic hazards for multiple input changes in combinational switching circuits, Information and Control, vol.20, issue.2, pp.114-224, 1972.
DOI : 10.1016/S0019-9958(72)90299-9

V. Bregier, Synthèse automatisée de circuits optimisés prouvés Quasi Insensibles aux Délais, 2007.

V. Bregier, B. Folco, L. Fesquet, and M. Renaudin, Modeling and synthesis of multi-rail multi-protocol QDI circuits, International Workshop on Logic Synthesis, 2004.
URL : https://hal.archives-ouvertes.fr/hal-01384270

S. M. Burns, General conditions for the decomposition of state holding elements, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1996.
DOI : 10.1109/ASYNC.1996.494437

T. A. Chu, Synthesis of self-timed VLSI circuits from Graph-theoretic specifications, 1987.

W. A. Clark, Macromodular computer systems, Proceedings of the April 18-20, 1967, spring joint computer conference on, AFIPS '67 (Spring), 1967.
DOI : 10.1145/1465482.1465536

C. Constantinescu, Trends and challenges in VLSI circuit reliability, IEEE Micro, vol.23, issue.4, pp.14-99, 2003.
DOI : 10.1109/MM.2003.1225959

J. Cortadella, M. Kishinevsky, S. M. Burns, A. Kondratyev, L. Lavagno et al., Lazy transition systems and asynchronous circuit synthesis with relative timing assumptions, LAVAGNO, and A. YAKOVLEV. Logic Synthesis of Asynchronous Controllers and Interfaces, pp.109-130, 2002.
DOI : 10.1109/43.980253

C. Jordi, M. Kishinevsky, A. Kondratyev, L. Lavagno, E. Pastor et al., Decomposition and technology mapping of speed-independent circuits using boolean relations, Proc. International Conf. Computer-Aided Design (ICCAD), 1997.

A. L. Davis, The architecture and system method of DDM-1 : A recursively-structured data driven machine, Fifth Annual Symposium on Computer Architecture, 1978.

G. De and . Micheli, Synthesis and Optimisation of Digital Circuits, 1994.

A. Dinh-duc, L. Fesquet, and M. Renaudin, Synthesis of QDI asynchronous circuits from DTL-style petri nets, 11th IEEE/ACM International Workshop on Logic and Synthesis, 2002.

A. V. Dinh-duc, Synthèse automatique de circuits asynchrones QDI, 2003.

R. Dreschler and B. Becker, Binary Decision Diagrams, Theory and Implementation, 1998.

E. B. Eichelberger, Hazard Detection in Combinational and Sequential Switching Circuits, IBM Journal of Research and Development, vol.9, issue.2, pp.90-99, 1965.
DOI : 10.1147/rd.92.0090

F. B. Endecott and S. B. Furber, Modelling and simulation of asynchronous system using the LARD hardware description language, Proc. of the 12th European Simulation Multiconference Society for Computer Simulation International, pp.39-43, 1994.

K. M. Fant, Logically Determined Design, 2005.
DOI : 10.1002/0471702897

M. Ferretti and P. A. Beerel, Single-track asynchronous pipeline templates using 1-of-N encoding, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition, pp.1008-1015, 2002.
DOI : 10.1109/DATE.2002.998423

M. Ferretti and P. A. Beerel, High Performance Asynchronous Design Using Single-Track Full-Buffer Standard Cells, IEEE Journal of Solid-State Circuits, vol.41, issue.6, pp.1444-1454, 2006.
DOI : 10.1109/JSSC.2006.874308

M. Ferretti, R. O. Ozdag, and P. A. Beerel, High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings., pp.95-105, 2004.
DOI : 10.1109/ASYNC.2004.1299291

B. Folco, Rapport de DEA : Génération automatique et optimisation de circuits QDI, 2003.

B. Folco, V. Bregier, L. Fesquet, and M. Renaudin, Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits, IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp.146-151, 2005.
DOI : 10.1007/978-0-387-73661-7_5
URL : https://hal.archives-ouvertes.fr/hal-00185940

R. M. Fuhrer, S. M. Nowick, M. Theobald, N. K. Jha, B. Lin et al., Minimalist : An environment for the synthesis, verification and testability of burst-mode asynchronous machines, 1999.

H. Van, G. , D. Baumann, K. Van, B. et al., An asynchronous low-power 80c51 microcontroller, Proc. International Symposium on Advanced Research in Asynchronous Circuits ans Systems (ASYNC), pp.96-107, 1998.

F. Germain, Sécurité cryptographique par la conception spécifique de circuits intégrés, 2006.

S. Guilley, P. Hoogvorst, Y. Mathieu, R. Pacalet, and J. Provost, CMOS structures suitable for secured hardware, Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004.
DOI : 10.1109/DATE.2004.1269113

S. Hauck, Asynchronous design methodologies: an overview, Proceedings of the IEEE, pp.69-93, 1995.
DOI : 10.1109/5.362752

Q. T. Ho, J. B. Rigaud, L. Fesquet, M. Renaudin, and R. Rolland, Implementing Asynchronous Circuits on LUT Based FPGAs, Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field Programmable Logic and Applications, pp.36-46, 2002.
DOI : 10.1007/3-540-46117-5_6
URL : https://hal.archives-ouvertes.fr/hal-00009602

C. A. Hoare, Communicating sequential processes, Communications of the ACM, vol.21, issue.8, pp.666-677, 1978.
DOI : 10.1145/359576.359585

C. Jeong and S. M. Nowick, Optmial technology mapping and cell merger for asynchronous threshold networks, 12th International Symposium on Asynchronous Circuits and Systems, pp.128-137, 2006.

J. Kessels, T. Kramer, G. Besten, A. Peeters, and V. Timm, Applying asynchronous circuits in contactless smart cards, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586), pp.36-44, 2000.
DOI : 10.1109/ASYNC.2000.836785

P. Kocher, J. Jaffe, and B. Jun, Differential Power Analysis, Lecture Notes in Computer Science, vol.1666, pp.388-397, 1999.
DOI : 10.1007/3-540-48405-1_25

A. Kondratyev, J. Cortadella, M. Kishinevsky, L. Lavagno, A. P. Yakovlev et al., Logic decomposition of speed-independent circuits Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes, Proceedings of the IEEE ACM/IEEE 33rd Design Automation Conference, pp.347-362, 1996.

Y. Kukimoto, R. K. Brayton, and P. Sawkar, Delay-optimal technology mapping by DAG covering, Proceedings of the 35th annual conference on Design automation conference , DAC '98, 1998.
DOI : 10.1145/277044.277142
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.32.2934

M. Lightart, K. M. Fant, R. Smith, A. Taubin, and A. Kondratyev, Asynchronous design using commercial HDL synthesis tool, Proc. of International Symposium on Asynchronous Circuits and Systems, pp.114-125, 2000.

F. Mailhot, G. De, and . Micheli, Technology mapping using Boolean matching and don't care sets, Proceedings of the European Design Automation Conference, 1990., EDAC., pp.212-216, 1990.
DOI : 10.1109/EDAC.1990.136647

A. Martin, Compiling communicating processes into delay-insensitive VLSI circuits, Distributed Computing, vol.20, issue.8, pp.226-234, 1986.
DOI : 10.1007/BF01660034

A. Martin, Programming in VLSI : From communicating processes to delay-insensitive circuits. Development in Concurrency and Communication, 1990.

A. Martin, A. Lines, R. Manohar, M. Nystroem, P. Penzes et al., The design of an asynchronous MIPS R3000 microprocessor, Proceedings Seventeenth Conference on Advanced Research in VLSI, pp.164-181, 1997.
DOI : 10.1109/ARVLSI.1997.634853

A. J. Martin, The Limitations to Delay-Insensitivity in Asynchronous Circuits, Advanced Research in VLSI, pp.263-278, 1990.
DOI : 10.1007/978-1-4612-4476-9_35

P. Maurine, J. B. Rigaud, F. Bouesse, G. Sicard, and M. Renaudin, Static Implementation of QDI Asynchronous Primitives, PATMOS : 13th International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.181-191, 2003.
DOI : 10.1007/978-3-540-39762-5_20
URL : https://hal.archives-ouvertes.fr/hal-01376724

P. Maurine, J. B. Rigaud, F. Bouesse, G. Sicard, and M. Renaudin, TAL : une bibliothèque de cellules pour le design de circuits asynchrones QDI, 4iemes journées Francophones d'Etudes Faible Tension, Faible Consommation, pp.41-49, 2003.

R. E. Miller, Sequential Circuits and Machines, volume 2 of Switching Theory, 1965.

Y. Monnet, Etude et modélisation de circuits résistants aux attaques non intrusives par injection de fautes, 2007.

S. M. Nowick, Automatic Synthesis of Burst-Mode Asynchronous Controllers, 1993.

R. O. Ozdag and P. A. Beerel, A channel based asynchronous low powerhigh performance standard-cell based sequential decoder implemented with QDI templates, 10th International Symposium on Asynchronous Circuits and Systems, pp.187-197, 2004.

D. Panyasak, Réduction de l'Emission Electromagnétique des Circuits Intégrés : L'Alternative Asynchrone, 2004.

C. A. Petri, Kommunikation mit automaten, 1962.

J. Quartana, Design of Asynchronous Network on Chip : application to GALS systems, 2004.
URL : https://hal.archives-ouvertes.fr/tel-00008830

A. Razafindraibe, Analyse et amélioration de la logique double-rail pour la conception de circuits sécurisés, 2006.

M. Renaudin, Asynchronous circuits and systems : a promising design alternative, Microelectronic Engineering, vol.54, issue.1-2, pp.133-149, 2000.
DOI : 10.1016/S0167-9317(00)80065-9
URL : https://hal.archives-ouvertes.fr/hal-00011193

M. Renaudin and J. Rigaud, Etat de l'art sur la conception des circuits asynchrones : perspectives pour l'intégration des systèmes complexes, 1998.

J. B. Rigaud, Spécification de bibliothèques pour la synthèse de circuits asynchrones, 2002.

D. Rios-arambula, A. Buhrig, G. Sicard, and M. Renaudin, On the use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits, Journal of Low Power Electronics, vol.2, issue.1, pp.45-55, 2006.
DOI : 10.1166/jolpe.2006.006

B. Schneier, Cryptographie appliquée, Vuibert Informatique, 2001.

P. Siegel, M. De-micheli, and D. L. Dill, Automatic technology mapping for generalized fundamental-mode asynchronous designs, Proceedings of the 30th international on Design automation conference , DAC '93, pp.61-67, 1993.
DOI : 10.1145/157485.164573

P. S. Siegel, Automatic Technology Mapping for Asynchronous Designs, 1995.

P. S. Siegel, G. De, and . Micheli, Decomposition methods for library binding of speedindependent asynchronous designs [85] K. SLIMANI. Une méthodologie de conception de circuits asynchrones à faible consommation d'énergie : application au microprocesseur MIPS, International Conference on Computer Aided Design, pp.558-565, 1994.

J. Sparso, J. Staunstrup, and M. Dantzer-sorensen, Design of delay insensitive circuits using multi-ring structures, Proceedings EURO-DAC '92: European Design Automation Conference, pp.15-20, 1992.
DOI : 10.1109/EURDAC.1992.246271

D. Stinson, Cryptographie : Théorie et Pratique, 1996.

K. Tiri, A. Moonmoon, and I. Verbauwhede, A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards, 28th European Solid-State Circuits Conference, 2002.

J. T. Udding, A formal model for defining and classifying delay-insensitive circuits and systems, Distributed Computing, vol.30, issue.2, pp.197-204, 1986.
DOI : 10.1007/BF01660032

S. H. Unger, Asynchronous Sequential Switching Circuits, IEEE Transactions on Systems, Man, and Cybernetics, vol.3, issue.3, 1969.
DOI : 10.1109/TSMC.1973.4309232

J. F. Wakerly, Digital Design : Principles and Pratices, 1994.

A. Yakovlev, L. Gomes, and L. Lavagno, Hardware Design and Petri Nets, 2000.
DOI : 10.1007/978-1-4757-3143-9

T. Yoneda, O. Hiroomi, and C. J. Myers, Synthesis of speed independent circuits based on decomposition, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings., pp.135-145, 2004.
DOI : 10.1109/ASYNC.2004.1299295

M. Zhao and S. S. Sapatnekar, A new structural pattern matching algorithm for technology mapping, Proceedings of the 38th conference on Design automation , DAC '01, pp.371-376, 2001.
DOI : 10.1145/378239.378526