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Optimisation conjointe de codes LDPC et de leurs architectures de décodage et mise en œuvre sur FPGA

Abstract : The introduction of Turbo-codes in the early 90's and, more generally the iterative principle, has deeply modified the methods for the design of communication systems. This breakthrough has also resurrected the Low Density Parity Check (LDPC) codes invented by R. Gallager in 1963. Advanced channel coding techniques such as Turbo-codes and LDPC, are now increasingly considered for introduction into communication systems and standards. This evolution towards industrialization motivates the definition of new flexible and efficient decoding architecture for LDPC codes. In this thesis, we focus our research on the iterative decoding of LDPC codes and their hardware implementation.
We first introduce basic concepts and notations for LDPC codes, which are necessary for a good comprehension. This introduction underlines the interest of jointly designing codes, decoding algorithm and architecture. From this perspective, a family of LDPC codes is described. We define some design rules to constrain the distance spectrum of the code. These constraints are introduced into a new algorithm for the design of the code working on a compact representation of the code graph.
A new decoding algorithm is also defined, taking advantage of the intrinsic properties of the code structure. Convergence of the decoding algorithm is increased compared to classical decoding algorithm for LDPC codes. Performance and flexibility of this algorithm is discussed. Different architectures are then described and studied. Some constraints on the codes are derived to target an architecture.
The last part of the thesis illustrates the implementation of one of the architectures discussed into a field-programmable gate array (FPGA). Performance and complexity measures are presented for various contexts, showing the interest of the concept for all these cases.
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Contributor : Jean-Baptiste Doré <>
Submitted on : Monday, May 12, 2008 - 12:31:33 PM
Last modification on : Monday, October 5, 2020 - 9:50:04 AM
Long-term archiving on: : Friday, November 25, 2016 - 11:01:00 PM


  • HAL Id : tel-00191155, version 2


Jean-Baptiste Doré. Optimisation conjointe de codes LDPC et de leurs architectures de décodage et mise en œuvre sur FPGA. Traitement du signal et de l'image [eess.SP]. INSA de Rennes, 2007. Français. ⟨tel-00191155v2⟩



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