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@. L. Anghel, D. Alexandrescu, and M. , Nicolaidis «Evaluation of Soft Error Tolerance Technique Based on Time and/or Space Redundancy, Proceedings of XIII Symposium on Integrated Circuits and Systems Design, 2000.

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@. D. Alexandrescu, L. Anghel, and M. Nicolaidis, Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing and Testable Applications, 2004.
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B. Gojman, H. Hsin, J. Liang, N. Nezhdanova, and J. Saini, Y-Junction carbon nanotube implementation of intramolecular electronic NAND gate, 2004.

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R. Leveugle and K. Hadjiat, Early prediction of SEU consequences through VHDL mutant generation, 6th European Conference on Radiation and its Effects on Components and Systems (RADECS), 2001.

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. Polytechnique-de-grenoble and T. Au-laboratoire, Intitulé : Les limites technologiques du silicium et tolérance aux fautes. Mention : Très Honorable avec les félicitations du jury Prix de la meilleure thèse de l'INPG en Microélectronique en, Thèse de Doctorat en Microélectronique, 2000.

. Sujet, Développement et réalisation d'un logiciel dédié à la simulation d'un milieu de vie artificiel

. Sujet, Etude de la fiabilité des MEMS/MOEMS face aux radiations ionisantes 6, 2005.

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S. Benhammadi, Master Pro CSINA, mars ? septembre, 2006.

C. Peng, Master Pro CSINA, mars ? septembre, 2006.

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M. Projet, . Eads, . Airbus, and . St-microelectronics, Responsable TIMA pour le projet PARACHUTE: Parasitic Extraction and Optimization for Efficient Microelectronic System Design and Application Partenaires : IZM (G), 2006.

T. and E. Janv, Projet de recherche EADS Projet de collaboration avec EADS CCR concernant l'étude de la sensibilité des FPGA Atmel face aux radiations Partenaires, 2005.

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P. Industriel, E. Partenaire, and . Projet, Méthodologie de remplacement des processeurs obsolètes, cas d'étude: Motorola 6800, validation des solutions de remplacement Partenaires: EDF (Electricité de France) et Laboratoire TIMA, 2001.

P. Européen, F. Ist-"-fracture-"-responsable, and T. Projet, Fault Tolerant Memories for High Defect Densities: Design and Validation of New Built in Self Repair Architectures Built in Nanotechnologies

I. Membre-d-'organisations-scientifiques-@bullet-membre and . @bullet-membre, Crete, Grece ? Vice General Chair IEEE International On Line Testing Symposium Lake Como, Italy ? General Chair IEEE International On Line Testing Symposium ? Publicity Chair IEEE International On Line Testing Symposium, ? Publicity Chair IEEE International On Line Testing Symposium ? Local Chair IEEE International On Line Testing Workshop, 2002.

@. Morocco, . Montevideo, and @. Uruguay, From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately? Next generation Design: Is EDA the Weakest Link? Process Variation Impact on Design and Test Collaborations on Research and Education between Europe and Latin America Future Directions Caused by Very Deep Submicron technologies, Participation à des panels dans des conférences internationales : ? « Design and Test Challenges in Deep Sub-micron Nanotechnologies Symposium on Integrated Circuits and Systems Design Blocks Hardening Techniques " , RADiation Effects on Component and Systems, 2001.

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C. Lazzari, L. Anghel, and R. Reis, A Transistor Placement Technique Using Genetic Algorithm And Analytical Programming selection of best papers from VLSI-SoC'05, Chapter, 2007.

I. O. Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Manneux et al., CNTFET modeling and reconfigurable logic circuit design, 2007.
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C. Lazzari, L. Anghel, and R. Reis, Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2007.
DOI : 10.1109/IOLTS.2006.48
URL : https://hal.archives-ouvertes.fr/hal-00143423

L. Anghel, M. Nicolaidis, and N. Achouri, Memory Defect Tolerance Architectures for Nanotechnologies, Journal of Electronic Testing and Testable Applications, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00102825

D. Alexandrescu, L. Anghel, and M. Nicolaidis, Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing and Testable Applications, 2004.
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M. Nicolaidis and L. , Concurrent checking for VLSI, Microelectronic Engineering, vol.49, issue.1-2, pp.139-156, 1999.
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C. Lazzari, R. Reis, and L. , Anghel, « Efficient Timing Closure with a Transistor Level Design Flow " , accepté à la conference VLSI SOC, 2007.

C. Grecu, L. Anghel, P. Pande, A. Ivanov, and R. Saleh, Essential Fault-Tolerance Metrics for NoC Infrastructures, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
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C. Rusu, A. Bougerol, L. Anghel, C. Weulerse, N. Buard et al., Multiple Event Transient Induced by Nuclear Reactions in CMOS Logic Cells, 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007.
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L. Anghel and M. Nicolaidis, Defects Tolerant Logic Gates for Unreliable Future Nanotechnologies », Invited Talk dans une session Speciale de la conférence IWANN (International Work-Conference on, Artificial Neural Networks), 2007.

T. Dang, L. Anghel, and R. Leveugle, CNTFET-based Logic Gates and Characteristics, accepté au IEEE Silicon Nanoelectronics Workshop, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00173965

V. Pouget, A. Douin, D. Lewis, L. Anghel, R. Leveugle et al., Tools and Methodology Development for Pulsed laser Fault Injection in SRAM based FPGA, Proceedings of 9 th IEEE Latin American Workshop, 2007.

A. Ammari, L. Anghel, R. Leveugle, C. Lazzari, and R. Reis, SET Fault Injection Methods in Analog Circuits: Case Study, Proceedings of 9 th IEEE Latin American Workshop, 2007.
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T. Dang, L. Anghel, and R. Leveugle, CNTFET-based Logic Gates and Simulation, Proceedings of IEEE International Design and Test, 2006.
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T. Dang, L. Anghel, and R. Leveugle, CNTFET basics and simulation, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., 2006.
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C. Lazzari, L. Anghel, and R. Reis, Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study, 12th IEEE International On-Line Testing Symposium (IOLTS'06), 2006.
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URL : https://hal.archives-ouvertes.fr/hal-00143423

G. Hubert, A. Bougerol, T. Carriere, N. Buard, and L. , Prediction of Transients Induced by neutrons, Protons in CMOS Combinational Logic Cells IEEE Inetrnational On Line Testing Symposium, 2006.
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C. Lazzari, L. Anghel, and R. A. Reis, A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming, Proceedings of IFIP VLSI ?SOC Conference, 2005.
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C. Lazzari, L. Anghel, and R. A. Reis, On implementing a soft error hardening technique by using an automatic layout generator: case study, 11th IEEE International On-Line Testing Symposium, 2005.
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L. Anghel, R. Leveugle, and P. Vanhauwaert, Evaluation of SET and SEU effects at multiple abstraction levels, 11th IEEE International On-Line Testing Symposium, 2005.
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URL : https://hal.archives-ouvertes.fr/hal-00015000

C. Lazzari, L. Anghel, and R. Reis, Soft Error Circuit Hardening Techniques Implementation Using an Automatic Layout Generator, Proceedings of IEEE Latin American Test Workshop, 2005.
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L. Anghel, E. Kolonis, and M. , Nicolaidis « Transient and Permanent Fault Tolerance Memory Cells for Unreliable Future Nanotechnologies», Proceedings of IEEE Latin American Test Workshop, 2005.

L. Anghel and D. Bhattacharia, Timing Closure: Hybrid Optimization to the Rescue, EE Time Asia, 2004.

L. Anghel, E. Sanchez, M. Sonza-reorda, G. Squillero, and R. Velazco, Coupling different methodologies to validate obsolete processors, Proceedings of Defect and Fault Tolerance in VLSI systems, 2004.

L. Anghel, M. Nicolaidis, and N. Achouri, Built In Self Repair Techniques for Based on ECC Codes to Cope with Memories Affected by High Defect Densities, Proceedings on IEEE VLSI Test Symposium Best Paper Award of IEEE VTS Conference, 2004.

L. Anghel, M. Nicolaidis, and N. Achouri, Evaluation of memory built-in self repair techniques for high defect density technologies, 10th IEEE Pacific Rim International Symposium on Dependable Computing, 2004. Proceedings., 2004.
DOI : 10.1109/PRDC.2004.1276581
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M. Nicolaidis, N. Achouri, and L. , Anghel, « A Memory Built-In Self Repair for High Defect Densities Based on Error Polarities » in Proceedings of 18 th , Defect and Fault Tolerance for VLSI Systems, 2003.

L. Anghel, R. Velazco, and S. Saleh, Validation of an Approach Dealing with Processor Obsolescence Defect and Fault Tolerance for VLSI Systems, Proceedings of 18 th, 2003.

M. Nicolaidis, N. Achouri, and L. , Anghel, « Memory Built In Self Repair for Nanotechnologies, Proceedings of IEEE 9 th International On Line Testing Symposium, 2003.

R. Velazco, L. Anghel, and S. Saleh, A methodology for test replacement solutions of obsolete processors, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., 2003.
DOI : 10.1109/OLT.2003.1214400
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D. Alexandrescu, L. Anghel, and M. , Nicolaidis, « New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs, Proceedings of 17 th , Defect and Fault Tolerance for VLSI Systems, 2002.

D. Alexandrescu, L. Anghel, and M. Nicolaidis, Simulating Single Event Transients in VDSM ICs for Ground Level Radiation, Journal of Electronic Testing, vol.20, issue.4, 2002.
DOI : 10.1023/B:JETT.0000039608.48856.33
URL : https://hal.archives-ouvertes.fr/hal-00013725

L. Anghel, D. Alexandrescu, and M. , Nicolaidis «Evaluation of Soft Error Tolerance Technique Based on Time and/or Space Redundancy, Proceedings of XIII Symposium on Integrated Circuits and Systems Design, 2000.

L. Anghel, M. Nicolaidis, and I. , Self-checking circuits versus realistic faults in very deep submicron, Proceedings 18th IEEE VLSI Test Symposium, pp.55-63, 2000.
DOI : 10.1109/VTEST.2000.843827
URL : https://hal.archives-ouvertes.fr/hal-00013754

L. Anghel and M. Nicolaidis, Cost Reduction and Evaluation of a Temporary Faults Detecting Technique, Proceeding of Design Automation and Test in Europe Best Paper Award of IEEE/ACM « Design, Automation and Test in Europe, pp.591-597, 2000.
URL : https://hal.archives-ouvertes.fr/hal-00013756

T. Calin, L. Anghel, and M. Nicolaidis, Built-in current sensor for IDDQ testing in deep submicron CMOS, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146), 1999.
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L. Anghel and M. Nicolaidis, Implementation and Evaluation of a Soft Error Detecting Technique, Proceedings of 5 th IEEE International On-Line Testing Workshop, 1999.
URL : https://hal.archives-ouvertes.fr/hal-01357768