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Habilitation à diriger des recherches

Conception Robuste dans les Technologies CMOS et post-CMOS

Abstract : Silicon technologies approach their physical limits in terms of size and power supply reduction, as well as increase of their speed. Approaching these limits, integrated circuits become more and more sensitives to different internal or external parasitical phenomena that lead to an important number of application errors. This manuscrit presents a summary of my recent research work that has been done in collaboration with my undergraduated and phD students. They concern robustness techniques to transient faults and permanent defects, targetting advanced below 32nm CMOS technologies and post CMOS technologies. Another research direction is dedicated to the application errors prediction techniques. Different abstraction level simulation techniques are presented, for digital and analog circuits. The last part of the manuscript presents a short summary of the most recent work, around the modeling and the simulation of carbon nanotubes aiming at a predictive analysis of fault free systems.
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Habilitation à diriger des recherches
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Contributor : Lucie Torella <>
Submitted on : Wednesday, November 7, 2007 - 4:35:35 PM
Last modification on : Friday, December 11, 2020 - 8:28:04 AM
Long-term archiving on: : Monday, April 12, 2010 - 1:36:54 AM


  • HAL Id : tel-00185993, version 1




Lorena Anghel. Conception Robuste dans les Technologies CMOS et post-CMOS. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2007. ⟨tel-00185993⟩



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