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Synthèse automatisée de circuits asynchrones optimisés prouvés quasi insensibles aux délais

Abstract : In an asynchronous circuit, the synchronization between the blocs is local: the constraints due to the clock do not apply. These circuits are more robust, modular, have less noise and a lower dynamic power consumption that asynchronous circuits. However, the lack of design tools for such circuits prevents them from spreading widely. This thesis aimed at developping an automatic synthesis technique targeting asynchronous quasi delay insensitive (QDI) circuits, which are particularly robust. The technique synthesizes a circuit totally decomposed in elemetary logical gates, which allows a later technology mapping. Moreover, a formal study done during this thesis proves that the circuits synthesized respect the constraint of quasi delay insensitivity. This synthesis technique was developped in the TAST project. Is has been validated on a set of test circuits.
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https://tel.archives-ouvertes.fr/tel-00178543
Contributor : Lucie Torella <>
Submitted on : Thursday, October 11, 2007 - 2:57:28 PM
Last modification on : Thursday, November 19, 2020 - 3:56:19 PM
Long-term archiving on: : Monday, September 24, 2012 - 1:16:49 PM

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  • HAL Id : tel-00178543, version 1

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V. Brégier. Synthèse automatisée de circuits asynchrones optimisés prouvés quasi insensibles aux délais. Micro et nanotechnologies/Microélectronique. Institut National Polytechnique de Grenoble - INPG, 2007. Français. ⟨tel-00178543⟩

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